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c20febdbb0
If building with -mcpu=native or any other setting which implies the current CPU has FP16 but with intrinsics disabled, we mistakenly try to use it even though convolution.hpp conditionally defines it correctly based on whether we should *use it*. convolution.cpp on the other hand was mismatched and trying to use it if the CPU supported it, even if not enabled in the build system. Make the guards match. Bug: https://bugs.gentoo.org/913031 Signed-off-by: Sam James <sam@gentoo.org>
122 lines
3.8 KiB
C++
122 lines
3.8 KiB
C++
// This file is part of OpenCV project.
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// It is subject to the license terms in the LICENSE file found in the top-level directory
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// of this distribution and at http://opencv.org/license.html.
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#ifndef OPENCV_FAST_CONVOLUTION_HPP
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#define OPENCV_FAST_CONVOLUTION_HPP
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#include "opencv2/core/hal/intrin.hpp"
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#ifndef CONV_PRAM
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#define CONV_PRAM
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#if CV_NEON && CV_NEON_AARCH64 // 32 registers.
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#define CONV_MR_FP32 4
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#define CONV_NR_FP32 28
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// The FP16 can only be supported by ARM64 and with FP16 FMA supported.
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#if defined(__ARM_FEATURE_FP16_VECTOR_ARITHMETIC) && CV_FP16 // check FP16 FMA.
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#define CONV_ARM_FP16 1
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#endif
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#ifdef CONV_ARM_FP16
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// Currently, only ARM 64 support FP16.
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#define CONV_MR_FP16 8
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#define CONV_NR_FP16 24
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typedef __fp16 float16_t; // Fix conflict between float16_t in arm_neon.h and float16_t in cvdef.h.
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#endif
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#elif CV_NEON // 16 registers.
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#define CONV_MR_FP32 4
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#define CONV_NR_FP32 12
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#else // SIMD 128, AVX or AVX2
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#define CONV_MR_FP32 4
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#define CONV_NR_FP32 24
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#endif
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enum {
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CONV_WINO_STEP=6,
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CONV_WINO_KSIZE=3,
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CONV_WINO_SIZE=CONV_WINO_STEP+CONV_WINO_KSIZE - 1, // 8
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CONV_WINO_AREA=CONV_WINO_SIZE*CONV_WINO_SIZE,
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};
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// NOTE that: CONV_TYPE_DEPTHWISE is for 3x3 depthwise conv, and others depthwise will be set as CONV_TYPE_DEPTHWISE_REMAIN.
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enum { CONV_TYPE_GENERIC=0, CONV_TYPE_DEPTHWISE=1, CONV_TYPE_WINOGRAD3X3=2, CONV_TYPE_DEPTHWISE_REMAIN=3 };
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enum { CONV_1D = 0, CONV_2D = 1, CONV_3D = 2 };
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#endif
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namespace cv {
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namespace dnn {
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struct FastConv
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{
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int ngroups;
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int K, C, Hk, Wk, Dk;
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int stride_h, stride_w, stride_d;
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int dilation_h, dilation_w, dilation_d;
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int pad_top, pad_bottom, pad_left, pad_right, pad_front, pad_behind;
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std::vector<float> weightsBuf; // For generic Conv 2D
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float* weightsBufPtr;
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std::vector<float> weightsWinoBuf; // For Winograd F(6x6, 3x3).
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float* weightsWinoBufPtr;
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std::vector<float> biasBuf;
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#if CV_NEON && CV_NEON_AARCH64 && CV_FP16
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std::vector<float16_t> weightsBuf_FP16;
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float16_t* weightsBufPtr_FP16;
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std::vector<float16_t> weightsWinoBuf_FP16;
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float16_t* weightsWinoBufPtr_FP16;
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#endif
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int conv_type;
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int conv_dim; // Flag for conv1d, conv2d, or conv3d.
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bool useFP16 = false; // Only ARMv8 is supported.
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#if CV_SIMD128
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bool useSIMD128 = true;
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#else
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bool useSIMD128 = false;
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#endif
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#if CV_NEON
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bool useNEON = checkHardwareSupport(CPU_NEON);
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#else
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bool useNEON = false;
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#endif
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bool useAVX = checkHardwareSupport(CPU_AVX);
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bool useAVX2 = checkHardwareSupport(CPU_AVX2);
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bool useRVV = checkHardwareSupport(CPU_RVV);
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};
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// return a FastConv instance.
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Ptr<FastConv> initFastConv(
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InputArray weightsMat,
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float* srcBias,
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int ngroups,
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int K, int C,
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const std::vector<size_t>& kernel_size,
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const std::vector<size_t>& strides,
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const std::vector<size_t>& dilations,
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const std::vector<size_t>& pads_begin,
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const std::vector<size_t>& pads_end,
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int conv_dim,
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const bool useFP16,
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bool useWinograd);
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// It contains different computing branches, like winograd, 1x1 conv.
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void runFastConv(InputArray _input, OutputArray _output, const Ptr<FastConv>& conv, int ntasks,
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const Ptr<ActivationLayer>& actLayer, const std::vector<float>& reluslope, bool fusedAdd);
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void runDepthwise(InputArray _input, OutputArray _output, const Ptr<FastConv>& conv, ActivationLayer* activ,
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const std::vector<float>& reluslope, bool fusedAdd);
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int runWinograd63(InputArray _input, InputArray _fusedAddMat, OutputArray _output, const Ptr<FastConv>& conv, int ntasks,
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float minval, float maxval, ActivationLayer* activ, bool ifMinMaxAct);
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} // namespace dnn
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} // namespace cv
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#endif //OPENCV_FAST_CONVOLUTION_HPP
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