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85923c8f30
Update zlib-ng to 2.2.1 #26113 Release: https://github.com/zlib-ng/zlib-ng/releases/tag/2.2.1 ARM diagnostics patch: https://github.com/zlib-ng/zlib-ng/pull/1774 ### Pull Request Readiness Checklist See details at https://github.com/opencv/opencv/wiki/How_to_contribute#making-a-good-pull-request - [x] I agree to contribute to the project under Apache 2 License. - [x] To the best of my knowledge, the proposed patch is not based on a code under GPL or another license that is incompatible with OpenCV - [x] The PR is proposed to the proper branch - [ ] There is a reference to the original bug report and related work - [ ] There is accuracy test, performance test and test data in opencv_extra repository, if applicable Patch to opencv_extra has the same branch name. - [ ] The feature is well documented and sample code can be built with the project CMake
116 lines
3.4 KiB
C
116 lines
3.4 KiB
C
/* x86_features.c - x86 feature check
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*
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* Copyright (C) 2013 Intel Corporation. All rights reserved.
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* Author:
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* Jim Kukunas
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*
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* For conditions of distribution and use, see copyright notice in zlib.h
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*/
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#include "zbuild.h"
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#include "x86_features.h"
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#ifdef _MSC_VER
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# include <intrin.h>
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#else
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// Newer versions of GCC and clang come with cpuid.h
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# include <cpuid.h>
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# ifdef X86_HAVE_XSAVE_INTRIN
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# if __GNUC__ == 8
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# include <xsaveintrin.h>
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# else
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# include <immintrin.h>
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# endif
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# endif
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#endif
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#include <string.h>
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static inline void cpuid(int info, unsigned* eax, unsigned* ebx, unsigned* ecx, unsigned* edx) {
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#ifdef _MSC_VER
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unsigned int registers[4];
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__cpuid((int *)registers, info);
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*eax = registers[0];
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*ebx = registers[1];
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*ecx = registers[2];
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*edx = registers[3];
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#else
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*eax = *ebx = *ecx = *edx = 0;
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__cpuid(info, *eax, *ebx, *ecx, *edx);
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#endif
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}
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static inline void cpuidex(int info, int subinfo, unsigned* eax, unsigned* ebx, unsigned* ecx, unsigned* edx) {
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#ifdef _MSC_VER
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unsigned int registers[4];
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__cpuidex((int *)registers, info, subinfo);
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*eax = registers[0];
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*ebx = registers[1];
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*ecx = registers[2];
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*edx = registers[3];
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#else
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*eax = *ebx = *ecx = *edx = 0;
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__cpuid_count(info, subinfo, *eax, *ebx, *ecx, *edx);
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#endif
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}
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static inline uint64_t xgetbv(unsigned int xcr) {
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#if defined(_MSC_VER) || defined(X86_HAVE_XSAVE_INTRIN)
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return _xgetbv(xcr);
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#else
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uint32_t eax, edx;
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__asm__ ( ".byte 0x0f, 0x01, 0xd0" : "=a"(eax), "=d"(edx) : "c"(xcr));
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return (uint64_t)(edx) << 32 | eax;
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#endif
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}
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void Z_INTERNAL x86_check_features(struct x86_cpu_features *features) {
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unsigned eax, ebx, ecx, edx;
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unsigned maxbasic;
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cpuid(0, &maxbasic, &ebx, &ecx, &edx);
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cpuid(1 /*CPU_PROCINFO_AND_FEATUREBITS*/, &eax, &ebx, &ecx, &edx);
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features->has_sse2 = edx & 0x4000000;
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features->has_ssse3 = ecx & 0x200;
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features->has_sse42 = ecx & 0x100000;
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features->has_pclmulqdq = ecx & 0x2;
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if (ecx & 0x08000000) {
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uint64_t xfeature = xgetbv(0);
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features->has_os_save_ymm = ((xfeature & 0x06) == 0x06);
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features->has_os_save_zmm = ((xfeature & 0xe6) == 0xe6);
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}
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if (maxbasic >= 7) {
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cpuidex(7, 0, &eax, &ebx, &ecx, &edx);
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// check BMI1 bit
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// Reference: https://software.intel.com/sites/default/files/article/405250/how-to-detect-new-instruction-support-in-the-4th-generation-intel-core-processor-family.pdf
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features->has_vpclmulqdq = ecx & 0x400;
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// check AVX2 bit if the OS supports saving YMM registers
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if (features->has_os_save_ymm) {
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features->has_avx2 = ebx & 0x20;
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}
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// check AVX512 bits if the OS supports saving ZMM registers
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if (features->has_os_save_zmm) {
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features->has_avx512f = ebx & 0x00010000;
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if (features->has_avx512f) {
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// According to the Intel Software Developer's Manual, AVX512F must be enabled too in order to enable
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// AVX512(DQ,BW,VL).
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features->has_avx512dq = ebx & 0x00020000;
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features->has_avx512bw = ebx & 0x40000000;
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features->has_avx512vl = ebx & 0x80000000;
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}
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features->has_avx512_common = features->has_avx512f && features->has_avx512dq && features->has_avx512bw \
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&& features->has_avx512vl;
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features->has_avx512vnni = ecx & 0x800;
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}
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}
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}
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