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https://github.com/tesseract-ocr/tesseract.git
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582 lines
28 KiB
CMake
582 lines
28 KiB
CMake
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# Determine the host CPU feature set and determine the best set of compiler
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# flags to enable all supported SIMD relevant features. Alternatively, the
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# target CPU can be explicitly selected (for generating more generic binaries
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# or for targeting a different system).
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# Compilers provide e.g. the -march=native flag to achieve a similar result.
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# This fails to address the need for building for a different microarchitecture
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# than the current host.
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# The script tries to deduce all settings from the model and family numbers of
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# the CPU instead of reading the CPUID flags from e.g. /proc/cpuinfo. This makes
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# the detection more independent from the CPUID code in the kernel (e.g. avx2 is
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# not listed on older kernels).
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#
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# Usage:
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# OptimizeForArchitecture()
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# If either of Vc_SSE_INTRINSICS_BROKEN, Vc_AVX_INTRINSICS_BROKEN,
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# Vc_AVX2_INTRINSICS_BROKEN is defined and set, the OptimizeForArchitecture
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# macro will consequently disable the relevant features via compiler flags.
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#=============================================================================
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# Copyright 2010-2016 Matthias Kretz <kretz@kde.org>
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#
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# Redistribution and use in source and binary forms, with or without
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# modification, are permitted provided that the following conditions are
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# met:
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#
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# * Redistributions of source code must retain the above copyright notice,
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# this list of conditions and the following disclaimer.
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# * Redistributions in binary form must reproduce the above copyright notice,
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# this list of conditions and the following disclaimer in the documentation
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# and/or other materials provided with the distribution.
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# * Neither the names of contributing organizations nor the
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# names of its contributors may be used to endorse or promote products
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# derived from this software without specific prior written permission.
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#
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# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDER AND CONTRIBUTORS ``AS IS''
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# AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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# ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHORS OR CONTRIBUTORS BE LIABLE FOR
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# ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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# DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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# SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
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# CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
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# OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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#=============================================================================
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get_filename_component(_currentDir "${CMAKE_CURRENT_LIST_FILE}" PATH)
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include("${_currentDir}/AddCompilerFlag.cmake")
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include(CheckIncludeFileCXX)
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macro(_my_find _list _value _ret)
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list(FIND ${_list} "${_value}" _found)
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if(_found EQUAL -1)
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set(${_ret} FALSE)
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else(_found EQUAL -1)
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set(${_ret} TRUE)
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endif(_found EQUAL -1)
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endmacro(_my_find)
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macro(AutodetectHostArchitecture)
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set(TARGET_ARCHITECTURE "generic")
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set(Vc_ARCHITECTURE_FLAGS)
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set(_vendor_id)
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set(_cpu_family)
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set(_cpu_model)
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if(CMAKE_SYSTEM_NAME STREQUAL "Linux")
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file(READ "/proc/cpuinfo" _cpuinfo)
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string(REGEX REPLACE ".*vendor_id[ \t]*:[ \t]+([a-zA-Z0-9_-]+).*" "\\1" _vendor_id "${_cpuinfo}")
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string(REGEX REPLACE ".*cpu family[ \t]*:[ \t]+([a-zA-Z0-9_-]+).*" "\\1" _cpu_family "${_cpuinfo}")
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string(REGEX REPLACE ".*model[ \t]*:[ \t]+([a-zA-Z0-9_-]+).*" "\\1" _cpu_model "${_cpuinfo}")
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string(REGEX REPLACE ".*flags[ \t]*:[ \t]+([^\n]+).*" "\\1" _cpu_flags "${_cpuinfo}")
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elseif(CMAKE_SYSTEM_NAME STREQUAL "Darwin")
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exec_program("/usr/sbin/sysctl -n machdep.cpu.vendor machdep.cpu.model machdep.cpu.family machdep.cpu.features" OUTPUT_VARIABLE _sysctl_output_string)
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string(REPLACE "\n" ";" _sysctl_output ${_sysctl_output_string})
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list(GET _sysctl_output 0 _vendor_id)
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list(GET _sysctl_output 1 _cpu_model)
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list(GET _sysctl_output 2 _cpu_family)
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list(GET _sysctl_output 3 _cpu_flags)
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string(TOLOWER "${_cpu_flags}" _cpu_flags)
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string(REPLACE "." "_" _cpu_flags "${_cpu_flags}")
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elseif(CMAKE_SYSTEM_NAME STREQUAL "Windows")
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get_filename_component(_vendor_id "[HKEY_LOCAL_MACHINE\\Hardware\\Description\\System\\CentralProcessor\\0;VendorIdentifier]" NAME CACHE)
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get_filename_component(_cpu_id "[HKEY_LOCAL_MACHINE\\Hardware\\Description\\System\\CentralProcessor\\0;Identifier]" NAME CACHE)
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mark_as_advanced(_vendor_id _cpu_id)
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string(REGEX REPLACE ".* Family ([0-9]+) .*" "\\1" _cpu_family "${_cpu_id}")
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string(REGEX REPLACE ".* Model ([0-9]+) .*" "\\1" _cpu_model "${_cpu_id}")
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endif(CMAKE_SYSTEM_NAME STREQUAL "Linux")
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if(_vendor_id STREQUAL "GenuineIntel")
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if(_cpu_family EQUAL 6)
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# taken from the Intel ORM
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# http://www.intel.com/content/www/us/en/processors/architectures-software-developer-manuals.html
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# CPUID Signature Values of Of Recent Intel Microarchitectures
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# 4E 5E | Skylake microarchitecture
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# 3D 47 56 | Broadwell microarchitecture
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# 3C 45 46 3F | Haswell microarchitecture
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# 3A 3E | Ivy Bridge microarchitecture
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# 2A 2D | Sandy Bridge microarchitecture
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# 25 2C 2F | Intel microarchitecture Westmere
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# 1A 1E 1F 2E | Intel microarchitecture Nehalem
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# 17 1D | Enhanced Intel Core microarchitecture
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# 0F | Intel Core microarchitecture
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#
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# Intel SDM Vol. 3C 35-1 / December 2016:
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# 57 | Xeon Phi 3200, 5200, 7200 [Knights Landing]
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# 85 | Future Xeon Phi
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# 8E 9E | 7th gen. Core [Kaby Lake]
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# 55 | Future Xeon [Skylake w/ AVX512]
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# 4E 5E | 6th gen. Core / E3 v5 [Skylake w/o AVX512]
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# 56 | Xeon D-1500 [Broadwell]
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# 4F | Xeon E5 v4, E7 v4, i7-69xx [Broadwell]
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# 47 | 5th gen. Core / Xeon E3 v4 [Broadwell]
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# 3D | M-5xxx / 5th gen. [Broadwell]
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# 3F | Xeon E5 v3, E7 v3, i7-59xx [Haswell-E]
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# 3C 45 46 | 4th gen. Core, Xeon E3 v3 [Haswell]
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# 3E | Xeon E5 v2, E7 v2, i7-49xx [Ivy Bridge-E]
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# 3A | 3rd gen. Core, Xeon E3 v2 [Ivy Bridge]
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# 2D | Xeon E5, i7-39xx [Sandy Bridge]
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# 2F | Xeon E7
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# 2A | Xeon E3, 2nd gen. Core [Sandy Bridge]
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# 2E | Xeon 7500, 6500 series
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# 25 2C | Xeon 3600, 5600 series, Core i7, i5 and i3
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#
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# Values from the Intel SDE:
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# 5C | Goldmont
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# 5A | Silvermont
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# 57 | Knights Landing
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# 66 | Cannonlake
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# 55 | Skylake Server
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# 4E | Skylake Client
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# 3C | Broadwell (likely a bug in the SDE)
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# 3C | Haswell
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if(_cpu_model EQUAL 87) # 57
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set(TARGET_ARCHITECTURE "knl") # Knights Landing
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elseif(_cpu_model EQUAL 92)
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set(TARGET_ARCHITECTURE "goldmont")
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elseif(_cpu_model EQUAL 90 OR _cpu_model EQUAL 76)
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set(TARGET_ARCHITECTURE "silvermont")
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elseif(_cpu_model EQUAL 102)
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set(TARGET_ARCHITECTURE "cannonlake")
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elseif(_cpu_model EQUAL 142 OR _cpu_model EQUAL 158) # 8E, 9E
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set(TARGET_ARCHITECTURE "kaby-lake")
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elseif(_cpu_model EQUAL 85) # 55
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set(TARGET_ARCHITECTURE "skylake-avx512")
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elseif(_cpu_model EQUAL 78 OR _cpu_model EQUAL 94) # 4E, 5E
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set(TARGET_ARCHITECTURE "skylake")
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elseif(_cpu_model EQUAL 61 OR _cpu_model EQUAL 71 OR _cpu_model EQUAL 79 OR _cpu_model EQUAL 86) # 3D, 47, 4F, 56
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set(TARGET_ARCHITECTURE "broadwell")
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elseif(_cpu_model EQUAL 60 OR _cpu_model EQUAL 69 OR _cpu_model EQUAL 70 OR _cpu_model EQUAL 63)
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set(TARGET_ARCHITECTURE "haswell")
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elseif(_cpu_model EQUAL 58 OR _cpu_model EQUAL 62)
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set(TARGET_ARCHITECTURE "ivy-bridge")
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elseif(_cpu_model EQUAL 42 OR _cpu_model EQUAL 45)
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set(TARGET_ARCHITECTURE "sandy-bridge")
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elseif(_cpu_model EQUAL 37 OR _cpu_model EQUAL 44 OR _cpu_model EQUAL 47)
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set(TARGET_ARCHITECTURE "westmere")
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elseif(_cpu_model EQUAL 26 OR _cpu_model EQUAL 30 OR _cpu_model EQUAL 31 OR _cpu_model EQUAL 46)
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set(TARGET_ARCHITECTURE "nehalem")
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elseif(_cpu_model EQUAL 23 OR _cpu_model EQUAL 29)
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set(TARGET_ARCHITECTURE "penryn")
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elseif(_cpu_model EQUAL 15)
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set(TARGET_ARCHITECTURE "merom")
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elseif(_cpu_model EQUAL 28)
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set(TARGET_ARCHITECTURE "atom")
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elseif(_cpu_model EQUAL 14)
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set(TARGET_ARCHITECTURE "core")
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elseif(_cpu_model LESS 14)
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message(WARNING "Your CPU (family ${_cpu_family}, model ${_cpu_model}) is not known. Auto-detection of optimization flags failed and will use the generic CPU settings with SSE2.")
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set(TARGET_ARCHITECTURE "generic")
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else()
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message(WARNING "Your CPU (family ${_cpu_family}, model ${_cpu_model}) is not known. Auto-detection of optimization flags failed and will use the 65nm Core 2 CPU settings.")
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set(TARGET_ARCHITECTURE "merom")
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endif()
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elseif(_cpu_family EQUAL 7) # Itanium (not supported)
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message(WARNING "Your CPU (Itanium: family ${_cpu_family}, model ${_cpu_model}) is not supported by OptimizeForArchitecture.cmake.")
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elseif(_cpu_family EQUAL 15) # NetBurst
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list(APPEND _available_vector_units_list "sse" "sse2")
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if(_cpu_model GREATER 2) # Not sure whether this must be 3 or even 4 instead
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list(APPEND _available_vector_units_list "sse" "sse2" "sse3")
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endif(_cpu_model GREATER 2)
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endif(_cpu_family EQUAL 6)
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elseif(_vendor_id STREQUAL "AuthenticAMD")
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if(_cpu_family EQUAL 23)
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set(TARGET_ARCHITECTURE "zen")
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elseif(_cpu_family EQUAL 22) # 16h
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set(TARGET_ARCHITECTURE "AMD 16h")
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elseif(_cpu_family EQUAL 21) # 15h
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if(_cpu_model LESS 2)
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set(TARGET_ARCHITECTURE "bulldozer")
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else()
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set(TARGET_ARCHITECTURE "piledriver")
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endif()
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elseif(_cpu_family EQUAL 20) # 14h
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set(TARGET_ARCHITECTURE "AMD 14h")
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elseif(_cpu_family EQUAL 18) # 12h
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elseif(_cpu_family EQUAL 16) # 10h
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set(TARGET_ARCHITECTURE "barcelona")
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elseif(_cpu_family EQUAL 15)
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set(TARGET_ARCHITECTURE "k8")
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if(_cpu_model GREATER 64) # I don't know the right number to put here. This is just a guess from the hardware I have access to
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set(TARGET_ARCHITECTURE "k8-sse3")
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endif(_cpu_model GREATER 64)
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endif()
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endif(_vendor_id STREQUAL "GenuineIntel")
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endmacro()
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macro(OptimizeForArchitecture)
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if("${CMAKE_SYSTEM_PROCESSOR}" MATCHES "(x86|AMD64)")
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OptimizeForArchitectureX86()
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else()
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message(STATUS "No support for auto-detection of the target instruction set/extension")
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set(TARGET_ARCHITECTURE "unused" CACHE STRING "CPU architecture to optimize for. (unused)")
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endif()
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endmacro()
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macro(OptimizeForArchitectureX86)
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set(TARGET_ARCHITECTURE "auto" CACHE STRING "CPU architecture to optimize for. \
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Using an incorrect setting here can result in crashes of the resulting binary because of invalid instructions used. \
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Setting the value to \"auto\" will try to optimize for the architecture where cmake is called. \
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Other supported values are: \"none\", \"generic\", \"core\", \"merom\" (65nm Core2), \
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\"penryn\" (45nm Core2), \"nehalem\", \"westmere\", \"sandy-bridge\", \"ivy-bridge\", \
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\"haswell\", \"broadwell\", \"skylake\", \"skylake-xeon\", \"kaby-lake\", \"cannonlake\", \"silvermont\", \
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\"goldmont\", \"knl\" (Knights Landing), \"atom\", \"k8\", \"k8-sse3\", \"barcelona\", \
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\"istanbul\", \"magny-cours\", \"bulldozer\", \"interlagos\", \"piledriver\", \
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\"AMD 14h\", \"AMD 16h\", \"zen\".")
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set(_force)
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if(NOT _last_target_arch STREQUAL "${TARGET_ARCHITECTURE}")
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message(STATUS "target changed from \"${_last_target_arch}\" to \"${TARGET_ARCHITECTURE}\"")
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set(_force FORCE)
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endif()
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set(_last_target_arch "${TARGET_ARCHITECTURE}" CACHE STRING "" FORCE)
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mark_as_advanced(_last_target_arch)
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string(TOLOWER "${TARGET_ARCHITECTURE}" TARGET_ARCHITECTURE)
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set(_march_flag_list)
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set(_available_vector_units_list)
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if(TARGET_ARCHITECTURE STREQUAL "auto")
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AutodetectHostArchitecture()
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message(STATUS "Detected CPU: ${TARGET_ARCHITECTURE}")
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endif(TARGET_ARCHITECTURE STREQUAL "auto")
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macro(_nehalem)
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list(APPEND _march_flag_list "nehalem")
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list(APPEND _march_flag_list "corei7")
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list(APPEND _march_flag_list "core2")
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list(APPEND _available_vector_units_list "sse" "sse2" "sse3" "ssse3" "sse4.1" "sse4.2")
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endmacro()
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macro(_westmere)
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list(APPEND _march_flag_list "westmere")
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_nehalem()
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endmacro()
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macro(_sandybridge)
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list(APPEND _march_flag_list "sandybridge")
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list(APPEND _march_flag_list "corei7-avx")
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_westmere()
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list(APPEND _available_vector_units_list "sse" "sse2" "sse3" "ssse3" "sse4.1" "sse4.2" "avx")
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endmacro()
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macro(_ivybridge)
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list(APPEND _march_flag_list "ivybridge")
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list(APPEND _march_flag_list "core-avx-i")
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_sandybridge()
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list(APPEND _available_vector_units_list "rdrnd" "f16c")
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endmacro()
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macro(_haswell)
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list(APPEND _march_flag_list "haswell")
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list(APPEND _march_flag_list "core-avx2")
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_ivybridge()
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list(APPEND _available_vector_units_list "avx2" "fma" "bmi" "bmi2")
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endmacro()
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macro(_broadwell)
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list(APPEND _march_flag_list "broadwell")
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_haswell()
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endmacro()
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macro(_skylake)
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list(APPEND _march_flag_list "skylake")
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_broadwell()
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endmacro()
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macro(_skylake_avx512)
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list(APPEND _march_flag_list "skylake-avx512")
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_skylake()
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list(APPEND _available_vector_units_list "avx512f" "avx512cd" "avx512dq" "avx512bw" "avx512vl")
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endmacro()
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macro(_cannonlake)
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list(APPEND _march_flag_list "cannonlake")
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_skylake_avx512()
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list(APPEND _available_vector_units_list "avx512ifma" "avx512vbmi")
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endmacro()
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macro(_knightslanding)
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list(APPEND _march_flag_list "knl")
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_broadwell()
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list(APPEND _available_vector_units_list "avx512f" "avx512pf" "avx512er" "avx512cd")
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endmacro()
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macro(_silvermont)
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list(APPEND _march_flag_list "silvermont")
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_westmere()
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list(APPEND _available_vector_units_list "rdrnd")
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endmacro()
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macro(_goldmont)
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||
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list(APPEND _march_flag_list "goldmont")
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||
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_silvermont()
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endmacro()
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||
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||
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if(TARGET_ARCHITECTURE STREQUAL "core")
|
||
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list(APPEND _march_flag_list "core2")
|
||
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list(APPEND _available_vector_units_list "sse" "sse2" "sse3")
|
||
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elseif(TARGET_ARCHITECTURE STREQUAL "merom")
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||
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list(APPEND _march_flag_list "merom")
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||
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list(APPEND _march_flag_list "core2")
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||
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list(APPEND _available_vector_units_list "sse" "sse2" "sse3" "ssse3")
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||
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elseif(TARGET_ARCHITECTURE STREQUAL "penryn")
|
||
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list(APPEND _march_flag_list "penryn")
|
||
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list(APPEND _march_flag_list "core2")
|
||
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list(APPEND _available_vector_units_list "sse" "sse2" "sse3" "ssse3")
|
||
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message(STATUS "Sadly the Penryn architecture exists in variants with SSE4.1 and without SSE4.1.")
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||
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if(_cpu_flags MATCHES "sse4_1")
|
||
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message(STATUS "SSE4.1: enabled (auto-detected from this computer's CPU flags)")
|
||
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list(APPEND _available_vector_units_list "sse4.1")
|
||
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else()
|
||
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message(STATUS "SSE4.1: disabled (auto-detected from this computer's CPU flags)")
|
||
|
endif()
|
||
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elseif(TARGET_ARCHITECTURE STREQUAL "knl")
|
||
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_knightslanding()
|
||
|
elseif(TARGET_ARCHITECTURE STREQUAL "cannonlake")
|
||
|
_cannonlake()
|
||
|
elseif(TARGET_ARCHITECTURE STREQUAL "kaby-lake")
|
||
|
_skylake()
|
||
|
elseif(TARGET_ARCHITECTURE STREQUAL "skylake-xeon" OR TARGET_ARCHITECTURE STREQUAL "skylake-avx512")
|
||
|
_skylake_avx512()
|
||
|
elseif(TARGET_ARCHITECTURE STREQUAL "skylake")
|
||
|
_skylake()
|
||
|
elseif(TARGET_ARCHITECTURE STREQUAL "broadwell")
|
||
|
_broadwell()
|
||
|
elseif(TARGET_ARCHITECTURE STREQUAL "haswell")
|
||
|
_haswell()
|
||
|
elseif(TARGET_ARCHITECTURE STREQUAL "ivy-bridge")
|
||
|
_ivybridge()
|
||
|
elseif(TARGET_ARCHITECTURE STREQUAL "sandy-bridge")
|
||
|
_sandybridge()
|
||
|
elseif(TARGET_ARCHITECTURE STREQUAL "westmere")
|
||
|
_westmere()
|
||
|
elseif(TARGET_ARCHITECTURE STREQUAL "nehalem")
|
||
|
_nehalem()
|
||
|
elseif(TARGET_ARCHITECTURE STREQUAL "goldmont")
|
||
|
_goldmont()
|
||
|
elseif(TARGET_ARCHITECTURE STREQUAL "silvermont")
|
||
|
_silvermont()
|
||
|
elseif(TARGET_ARCHITECTURE STREQUAL "atom")
|
||
|
list(APPEND _march_flag_list "atom")
|
||
|
list(APPEND _march_flag_list "core2")
|
||
|
list(APPEND _available_vector_units_list "sse" "sse2" "sse3" "ssse3")
|
||
|
elseif(TARGET_ARCHITECTURE STREQUAL "k8")
|
||
|
list(APPEND _march_flag_list "k8")
|
||
|
list(APPEND _available_vector_units_list "sse" "sse2")
|
||
|
elseif(TARGET_ARCHITECTURE STREQUAL "k8-sse3")
|
||
|
list(APPEND _march_flag_list "k8-sse3")
|
||
|
list(APPEND _march_flag_list "k8")
|
||
|
list(APPEND _available_vector_units_list "sse" "sse2" "sse3")
|
||
|
elseif(TARGET_ARCHITECTURE STREQUAL "AMD 16h")
|
||
|
list(APPEND _march_flag_list "btver2")
|
||
|
list(APPEND _march_flag_list "btver1")
|
||
|
list(APPEND _available_vector_units_list "sse" "sse2" "sse3" "ssse3" "sse4a" "sse4.1" "sse4.2" "avx" "f16c")
|
||
|
elseif(TARGET_ARCHITECTURE STREQUAL "AMD 14h")
|
||
|
list(APPEND _march_flag_list "btver1")
|
||
|
list(APPEND _available_vector_units_list "sse" "sse2" "sse3" "ssse3" "sse4a")
|
||
|
elseif(TARGET_ARCHITECTURE STREQUAL "zen")
|
||
|
list(APPEND _march_flag_list "znver1")
|
||
|
_skylake()
|
||
|
list(APPEND _available_vector_units_list "sse4a")
|
||
|
elseif(TARGET_ARCHITECTURE STREQUAL "piledriver")
|
||
|
list(APPEND _march_flag_list "bdver2")
|
||
|
list(APPEND _march_flag_list "bdver1")
|
||
|
list(APPEND _march_flag_list "bulldozer")
|
||
|
list(APPEND _march_flag_list "barcelona")
|
||
|
list(APPEND _march_flag_list "core2")
|
||
|
list(APPEND _available_vector_units_list "sse" "sse2" "sse3" "ssse3" "sse4a" "sse4.1" "sse4.2" "avx" "xop" "fma4" "fma" "f16c")
|
||
|
elseif(TARGET_ARCHITECTURE STREQUAL "interlagos")
|
||
|
list(APPEND _march_flag_list "bdver1")
|
||
|
list(APPEND _march_flag_list "bulldozer")
|
||
|
list(APPEND _march_flag_list "barcelona")
|
||
|
list(APPEND _march_flag_list "core2")
|
||
|
list(APPEND _available_vector_units_list "sse" "sse2" "sse3" "ssse3" "sse4a" "sse4.1" "sse4.2" "avx" "xop" "fma4")
|
||
|
elseif(TARGET_ARCHITECTURE STREQUAL "bulldozer")
|
||
|
list(APPEND _march_flag_list "bdver1")
|
||
|
list(APPEND _march_flag_list "bulldozer")
|
||
|
list(APPEND _march_flag_list "barcelona")
|
||
|
list(APPEND _march_flag_list "core2")
|
||
|
list(APPEND _available_vector_units_list "sse" "sse2" "sse3" "ssse3" "sse4a" "sse4.1" "sse4.2" "avx" "xop" "fma4")
|
||
|
elseif(TARGET_ARCHITECTURE STREQUAL "barcelona")
|
||
|
list(APPEND _march_flag_list "barcelona")
|
||
|
list(APPEND _march_flag_list "core2")
|
||
|
list(APPEND _available_vector_units_list "sse" "sse2" "sse3" "sse4a")
|
||
|
elseif(TARGET_ARCHITECTURE STREQUAL "istanbul")
|
||
|
list(APPEND _march_flag_list "barcelona")
|
||
|
list(APPEND _march_flag_list "core2")
|
||
|
list(APPEND _available_vector_units_list "sse" "sse2" "sse3" "sse4a")
|
||
|
elseif(TARGET_ARCHITECTURE STREQUAL "magny-cours")
|
||
|
list(APPEND _march_flag_list "barcelona")
|
||
|
list(APPEND _march_flag_list "core2")
|
||
|
list(APPEND _available_vector_units_list "sse" "sse2" "sse3" "sse4a")
|
||
|
elseif(TARGET_ARCHITECTURE STREQUAL "generic")
|
||
|
list(APPEND _march_flag_list "generic")
|
||
|
elseif(TARGET_ARCHITECTURE STREQUAL "none")
|
||
|
# add this clause to remove it from the else clause
|
||
|
else(TARGET_ARCHITECTURE STREQUAL "core")
|
||
|
message(FATAL_ERROR "Unknown target architecture: \"${TARGET_ARCHITECTURE}\". Please set TARGET_ARCHITECTURE to a supported value.")
|
||
|
endif(TARGET_ARCHITECTURE STREQUAL "core")
|
||
|
|
||
|
if(NOT TARGET_ARCHITECTURE STREQUAL "none")
|
||
|
set(_disable_vector_unit_list)
|
||
|
set(_enable_vector_unit_list)
|
||
|
if(DEFINED Vc_AVX_INTRINSICS_BROKEN AND Vc_AVX_INTRINSICS_BROKEN)
|
||
|
UserWarning("AVX disabled per default because of old/broken toolchain")
|
||
|
set(_avx_broken true)
|
||
|
set(_avx2_broken true)
|
||
|
set(_fma4_broken true)
|
||
|
set(_xop_broken true)
|
||
|
else()
|
||
|
set(_avx_broken false)
|
||
|
if(DEFINED Vc_FMA4_INTRINSICS_BROKEN AND Vc_FMA4_INTRINSICS_BROKEN)
|
||
|
UserWarning("FMA4 disabled per default because of old/broken toolchain")
|
||
|
set(_fma4_broken true)
|
||
|
else()
|
||
|
set(_fma4_broken false)
|
||
|
endif()
|
||
|
if(DEFINED Vc_XOP_INTRINSICS_BROKEN AND Vc_XOP_INTRINSICS_BROKEN)
|
||
|
UserWarning("XOP disabled per default because of old/broken toolchain")
|
||
|
set(_xop_broken true)
|
||
|
else()
|
||
|
set(_xop_broken false)
|
||
|
endif()
|
||
|
if(DEFINED Vc_AVX2_INTRINSICS_BROKEN AND Vc_AVX2_INTRINSICS_BROKEN)
|
||
|
UserWarning("AVX2 disabled per default because of old/broken toolchain")
|
||
|
set(_avx2_broken true)
|
||
|
else()
|
||
|
set(_avx2_broken false)
|
||
|
endif()
|
||
|
endif()
|
||
|
|
||
|
macro(_enable_or_disable _name _flag _documentation _broken)
|
||
|
if(_broken)
|
||
|
set(_found false)
|
||
|
else()
|
||
|
_my_find(_available_vector_units_list "${_flag}" _found)
|
||
|
endif()
|
||
|
set(USE_${_name} ${_found} CACHE BOOL "${documentation}" ${_force})
|
||
|
mark_as_advanced(USE_${_name})
|
||
|
if(USE_${_name})
|
||
|
list(APPEND _enable_vector_unit_list "${_flag}")
|
||
|
else()
|
||
|
list(APPEND _disable_vector_unit_list "${_flag}")
|
||
|
endif()
|
||
|
endmacro()
|
||
|
_enable_or_disable(SSE2 "sse2" "Use SSE2. If SSE2 instructions are not enabled the SSE implementation will be disabled." false)
|
||
|
_enable_or_disable(SSE3 "sse3" "Use SSE3. If SSE3 instructions are not enabled they will be emulated." false)
|
||
|
_enable_or_disable(SSSE3 "ssse3" "Use SSSE3. If SSSE3 instructions are not enabled they will be emulated." false)
|
||
|
_enable_or_disable(SSE4_1 "sse4.1" "Use SSE4.1. If SSE4.1 instructions are not enabled they will be emulated." false)
|
||
|
_enable_or_disable(SSE4_2 "sse4.2" "Use SSE4.2. If SSE4.2 instructions are not enabled they will be emulated." false)
|
||
|
_enable_or_disable(SSE4a "sse4a" "Use SSE4a. If SSE4a instructions are not enabled they will be emulated." false)
|
||
|
_enable_or_disable(AVX "avx" "Use AVX. This will all floating-point vector sizes relative to SSE." _avx_broken)
|
||
|
_enable_or_disable(FMA "fma" "Use FMA." _avx_broken)
|
||
|
_enable_or_disable(BMI2 "bmi2" "Use BMI2." _avx_broken)
|
||
|
_enable_or_disable(AVX2 "avx2" "Use AVX2. This will double all of the vector sizes relative to SSE." _avx2_broken)
|
||
|
_enable_or_disable(XOP "xop" "Use XOP." _xop_broken)
|
||
|
_enable_or_disable(FMA4 "fma4" "Use FMA4." _fma4_broken)
|
||
|
_enable_or_disable(AVX512F "avx512f" "Use AVX512F. This will double all floating-point vector sizes relative to AVX2." false)
|
||
|
_enable_or_disable(AVX512VL "avx512vl" "Use AVX512VL. This enables 128- and 256-bit vector length instructions with EVEX coding (improved write-masking & more vector registers)." _avx2_broken)
|
||
|
_enable_or_disable(AVX512PF "avx512pf" "Use AVX512PF. This enables prefetch instructions for gathers and scatters." false)
|
||
|
_enable_or_disable(AVX512ER "avx512er" "Use AVX512ER. This enables exponential and reciprocal instructions." false)
|
||
|
_enable_or_disable(AVX512CD "avx512cd" "Use AVX512CD." false)
|
||
|
_enable_or_disable(AVX512DQ "avx512dq" "Use AVX512DQ." false)
|
||
|
_enable_or_disable(AVX512BW "avx512bw" "Use AVX512BW." false)
|
||
|
_enable_or_disable(AVX512IFMA "avx512ifma" "Use AVX512IFMA." false)
|
||
|
_enable_or_disable(AVX512VBMI "avx512vbmi" "Use AVX512VBMI." false)
|
||
|
|
||
|
if(MSVC)
|
||
|
# MSVC on 32 bit can select /arch:SSE2 (since 2010 also /arch:AVX)
|
||
|
# MSVC on 64 bit cannot select anything (should have changed with MSVC 2010)
|
||
|
_my_find(_enable_vector_unit_list "avx2" _found)
|
||
|
if(_found)
|
||
|
AddCompilerFlag("/arch:AVX2" CXX_FLAGS Vc_ARCHITECTURE_FLAGS CXX_RESULT _found)
|
||
|
endif()
|
||
|
if(NOT _found)
|
||
|
_my_find(_enable_vector_unit_list "avx" _found)
|
||
|
if(_found)
|
||
|
AddCompilerFlag("/arch:AVX" CXX_FLAGS Vc_ARCHITECTURE_FLAGS CXX_RESULT _found)
|
||
|
endif()
|
||
|
endif()
|
||
|
if(NOT _found)
|
||
|
_my_find(_enable_vector_unit_list "sse2" _found)
|
||
|
if(_found)
|
||
|
AddCompilerFlag("/arch:SSE2" CXX_FLAGS Vc_ARCHITECTURE_FLAGS)
|
||
|
endif()
|
||
|
endif()
|
||
|
foreach(_flag ${_enable_vector_unit_list})
|
||
|
string(TOUPPER "${_flag}" _flag)
|
||
|
string(REPLACE "." "_" _flag "__${_flag}__")
|
||
|
add_definitions("-D${_flag}")
|
||
|
endforeach(_flag)
|
||
|
elseif(CMAKE_CXX_COMPILER MATCHES "/(icpc|icc)$") # ICC (on Linux)
|
||
|
set(OFA_map_knl "-xMIC-AVX512")
|
||
|
set(OFA_map_cannonlake "-xCORE-AVX512")
|
||
|
set(OFA_map_skylake-avx512 "-xCORE-AVX512")
|
||
|
set(OFA_map_skylake "-xCORE-AVX2")
|
||
|
set(OFA_map_broadwell "-xCORE-AVX2")
|
||
|
set(OFA_map_haswell "-xCORE-AVX2")
|
||
|
set(OFA_map_ivybridge "-xCORE-AVX-I")
|
||
|
set(OFA_map_sandybridge "-xAVX")
|
||
|
set(OFA_map_westmere "-xSSE4.2")
|
||
|
set(OFA_map_nehalem "-xSSE4.2")
|
||
|
set(OFA_map_penryn "-xSSSE3")
|
||
|
set(OFA_map_merom "-xSSSE3")
|
||
|
set(OFA_map_core2 "-xSSE3")
|
||
|
set(_ok FALSE)
|
||
|
foreach(arch ${_march_flag_list})
|
||
|
if(DEFINED OFA_map_${arch})
|
||
|
AddCompilerFlag(${OFA_map_${arch}} CXX_FLAGS Vc_ARCHITECTURE_FLAGS CXX_RESULT _ok)
|
||
|
if(_ok)
|
||
|
break()
|
||
|
endif()
|
||
|
endif()
|
||
|
endforeach()
|
||
|
if(NOT _ok)
|
||
|
# This is the Intel compiler, so SSE2 is a very reasonable baseline.
|
||
|
message(STATUS "Did not recognize the requested architecture flag, falling back to SSE2")
|
||
|
AddCompilerFlag("-xSSE2" CXX_FLAGS Vc_ARCHITECTURE_FLAGS)
|
||
|
endif()
|
||
|
else() # not MSVC and not ICC => GCC, Clang, Open64
|
||
|
foreach(_flag ${_march_flag_list})
|
||
|
AddCompilerFlag("-march=${_flag}" CXX_RESULT _good CXX_FLAGS Vc_ARCHITECTURE_FLAGS)
|
||
|
if(_good)
|
||
|
break()
|
||
|
endif(_good)
|
||
|
endforeach(_flag)
|
||
|
foreach(_flag ${_enable_vector_unit_list})
|
||
|
AddCompilerFlag("-m${_flag}" CXX_RESULT _result)
|
||
|
if(_result)
|
||
|
set(_header FALSE)
|
||
|
if(_flag STREQUAL "sse3")
|
||
|
set(_header "pmmintrin.h")
|
||
|
elseif(_flag STREQUAL "ssse3")
|
||
|
set(_header "tmmintrin.h")
|
||
|
elseif(_flag STREQUAL "sse4.1")
|
||
|
set(_header "smmintrin.h")
|
||
|
elseif(_flag STREQUAL "sse4.2")
|
||
|
set(_header "smmintrin.h")
|
||
|
elseif(_flag STREQUAL "sse4a")
|
||
|
set(_header "ammintrin.h")
|
||
|
elseif(_flag STREQUAL "avx")
|
||
|
set(_header "immintrin.h")
|
||
|
elseif(_flag STREQUAL "avx2")
|
||
|
set(_header "immintrin.h")
|
||
|
elseif(_flag STREQUAL "fma4")
|
||
|
set(_header "x86intrin.h")
|
||
|
elseif(_flag STREQUAL "xop")
|
||
|
set(_header "x86intrin.h")
|
||
|
endif()
|
||
|
set(_resultVar "HAVE_${_header}")
|
||
|
string(REPLACE "." "_" _resultVar "${_resultVar}")
|
||
|
if(_header)
|
||
|
CHECK_INCLUDE_FILE_CXX("${_header}" ${_resultVar} "-m${_flag}")
|
||
|
if(NOT ${_resultVar})
|
||
|
set(_useVar "USE_${_flag}")
|
||
|
string(TOUPPER "${_useVar}" _useVar)
|
||
|
string(REPLACE "." "_" _useVar "${_useVar}")
|
||
|
message(STATUS "disabling ${_useVar} because ${_header} is missing")
|
||
|
set(${_useVar} FALSE)
|
||
|
list(APPEND _disable_vector_unit_list "${_flag}")
|
||
|
endif()
|
||
|
endif()
|
||
|
if(NOT _header OR ${_resultVar})
|
||
|
list(APPEND Vc_ARCHITECTURE_FLAGS "-m${_flag}")
|
||
|
endif()
|
||
|
endif()
|
||
|
endforeach(_flag)
|
||
|
foreach(_flag ${_disable_vector_unit_list})
|
||
|
AddCompilerFlag("-mno-${_flag}" CXX_FLAGS Vc_ARCHITECTURE_FLAGS)
|
||
|
endforeach(_flag)
|
||
|
endif()
|
||
|
endif()
|
||
|
endmacro()
|