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https://github.com/cesanta/mongoose.git
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96 lines
4.3 KiB
C
96 lines
4.3 KiB
C
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// Copyright (c) 2023 Cesanta Software Limited
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// All rights reserved
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// https://cache.nxp.com/secured/assets/documents/en/reference-manual/IMXRT1060XRM.pdf
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// https://cache.nxp.com/secured/assets/documents/en/user-guide/MIMXRT1060EVKBUM.pdf
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#pragma once
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#include "MIMXRT1062.h"
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#include "board.h"
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#include "peripherals.h"
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#include "pin_mux.h"
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#include "clock_config.h"
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#include "fsl_iomuxc.h"
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static inline void ethernet_init(void) {
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IOMUXC_SetPinMux(IOMUXC_GPIO_B1_10_ENET_REF_CLK, 1U);
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//
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IOMUXC_SetPinConfig(IOMUXC_GPIO_AD_B0_09_GPIO1_IO09, 0xB0A9U);
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IOMUXC_SetPinConfig(IOMUXC_GPIO_AD_B0_10_GPIO1_IO10, 0xB0A9U);
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IOMUXC_SetPinConfig(IOMUXC_GPIO_B1_04_ENET_RX_DATA00, 0xB0E9U);
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IOMUXC_SetPinConfig(IOMUXC_GPIO_B1_05_ENET_RX_DATA01, 0xB0E9U);
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IOMUXC_SetPinConfig(IOMUXC_GPIO_B1_06_ENET_RX_EN, 0xB0E9U);
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IOMUXC_SetPinConfig(IOMUXC_GPIO_B1_07_ENET_TX_DATA00, 0xB0E9U);
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IOMUXC_SetPinConfig(IOMUXC_GPIO_B1_08_ENET_TX_DATA01, 0xB0E9U);
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IOMUXC_SetPinConfig(IOMUXC_GPIO_B1_09_ENET_TX_EN, 0xB0E9U);
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IOMUXC_SetPinConfig(IOMUXC_GPIO_B1_10_ENET_REF_CLK, 0xB0E9U);
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IOMUXC_SetPinConfig(IOMUXC_GPIO_B1_11_ENET_RX_ER, 0xB0E9U);
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IOMUXC_SetPinConfig(IOMUXC_GPIO_EMC_40_ENET_MDC, 0xB0E9U);
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IOMUXC_SetPinConfig(IOMUXC_GPIO_EMC_41_ENET_MDIO, 0xB0E9U);
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//
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IOMUXC_EnableMode(IOMUXC_GPR, kIOMUXC_GPR_ENET1TxClkOutputDir, true);
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gpio_pin_config_t gpio_config = {kGPIO_DigitalOutput, 0, kGPIO_NoIntmode};
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GPIO_PinInit(GPIO1, 9, &gpio_config);
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GPIO_PinInit(GPIO1, 10, &gpio_config);
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GPIO_PinWrite(GPIO1, 9, 0); // reset PHY
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GPIO_PinWrite(GPIO1, 10, 1); // prevent NAND_TREE
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SDK_DelayAtLeastUs(10000, CLOCK_GetFreq(kCLOCK_CpuClk)); // keep PHY RST low for a while
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GPIO_PinWrite(GPIO1, 9, 1); // deassert RST
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CLOCK_EnableClock(kCLOCK_Enet);
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NVIC_EnableIRQ(ENET_IRQn); // Setup Ethernet IRQ handler
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}
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// Helper macro for MAC generation, byte reads not allowed
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#define GENERATE_LOCALLY_ADMINISTERED_MAC() \
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{ \
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2, OCOTP->CFG0 & 255, (OCOTP->CFG0 >> 10) & 255, \
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((OCOTP->CFG0 >> 19) ^ (OCOTP->CFG1 >> 19)) & 255, \
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(OCOTP->CFG1 >> 10) & 255, OCOTP->CFG1 & 255 \
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}
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// NOTE: You can fuse your own MAC and read it from OCOTP->MAC0, OCOTP->MAC1,
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// OCOTP->MAC2
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// For internal testing purposes
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#ifdef UART_DEBUG
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#define BIT(x) (1UL << (x))
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#define SETBITS(R, CLEARMASK, SETMASK) (R) = ((R) & ~(CLEARMASK)) | (SETMASK)
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// 14.5 Table 14-4: uart_clk_root
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// see sysinit.c for clocks, (14.7.9: defaults to pll3_80m = PLL3/6/1 = 80MHz)
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static inline void test_init(void) {
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LPUART_Type *uart = LPUART3; // hardcode to UART3 GPIO_AD_B1_06,07
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uint32_t freq = 80000000; // uart_clk_root frequency
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CCM_ANALOG->PLL_USB1 |= CCM_ANALOG_PLL_USB1_POWER_MASK; // Power PLL on
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while ((CCM_ANALOG->PLL_USB1 & CCM_ANALOG_PLL_USB1_LOCK_MASK) == 0)
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(void) 0; // wait until it is stable
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CCM_ANALOG->PLL_USB1 &= ~CCM_ANALOG_PLL_USB1_BYPASS_MASK; // Disable Bypass (switch to PLL)
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CCM->CSCDR1 &= ~(CCM_CSCDR1_UART_CLK_SEL_MASK | CCM_CSCDR1_UART_CLK_PODF_MASK);
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CLOCK_EnableClock(kCLOCK_Lpuart3);
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IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B1_06_LPUART3_TX, 0U);
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IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B1_07_LPUART3_RX, 0U);
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IOMUXC_SetPinConfig(IOMUXC_GPIO_AD_B1_06_LPUART3_TX, 0x10B0U);
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IOMUXC_SetPinConfig(IOMUXC_GPIO_AD_B1_07_LPUART3_RX, 0x10B0U);
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uart->GLOBAL |= LPUART_GLOBAL_RST_MASK; // reset, CTRL = 0, defaults
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uart->GLOBAL &= ~LPUART_GLOBAL_RST_MASK;
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SETBITS(uart->BAUD,
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LPUART_BAUD_OSR_MASK | LPUART_BAUD_SBR_MASK | LPUART_BAUD_SBNS_MASK,
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LPUART_BAUD_OSR(16 - 1) |
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LPUART_BAUD_SBR(freq / (16 * 115200))); // Rx sample at 16x
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SETBITS(uart->CTRL,
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LPUART_CTRL_PE_MASK | LPUART_CTRL_M_MASK | LPUART_CTRL_ILT_MASK |
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LPUART_CTRL_IDLECFG_MASK,
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LPUART_CTRL_IDLECFG(1) | LPUART_CTRL_ILT(1) |
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LPUART_BAUD_SBNS(0)); // no parity, idle 2 chars after 1 stop bit
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uart->CTRL |= LPUART_CTRL_TE_MASK | LPUART_CTRL_RE_MASK;
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}
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static inline void uart_write_byte(LPUART_Type *uart, uint8_t byte) {
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uart->DATA = byte;
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while ((uart->STAT & LPUART_STAT_TDRE_MASK) == 0) (void) 0;
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}
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static inline void uart_write_buf(LPUART_Type *uart, char *buf, size_t len) {
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while (len-- > 0) uart_write_byte(uart, *(uint8_t *) buf++);
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}
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#else
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#define test_init()
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#endif
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