mirror of
https://github.com/cesanta/mongoose.git
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52 lines
2.5 KiB
Plaintext
52 lines
2.5 KiB
Plaintext
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/*
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* GENERATED FILE - DO NOT EDIT
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* Copyright 2008-2013 Code Red Technologies Ltd,
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* Copyright 2013-2024 NXP
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* Generated linker script file for MIMXRT1062xxxxB
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* Created from memory.ldt by FMCreateLinkMemory
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* Using Freemarker v2.3.30
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* MCUXpresso IDE v11.8.1 [Build 1197] [2023-10-27] on Jan 5, 2024, 8:59:47 PM
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*/
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MEMORY
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{
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/* Define each memory region */
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BOARD_FLASH (rx) : ORIGIN = 0x60000000, LENGTH = 0x800000 /* 8M bytes (alias Flash) */
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SRAM_DTC (rwx) : ORIGIN = 0x20000000, LENGTH = 0x20000 /* 128K bytes (alias RAM) */
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SRAM_ITC (rwx) : ORIGIN = 0x0, LENGTH = 0x20000 /* 128K bytes (alias RAM2) */
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SRAM_OC2 (rwx) : ORIGIN = 0x20200000, LENGTH = 0x80000 /* 512K bytes (alias RAM3) */
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SRAM_OC (rwx) : ORIGIN = 0x20280000, LENGTH = 0x40000 /* 256K bytes (alias RAM4) */
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BOARD_SDRAM (rwx) : ORIGIN = 0x80000000, LENGTH = 0x1e00000 /* 30M bytes (alias RAM5) */
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NCACHE_REGION (rwx) : ORIGIN = 0x81e00000, LENGTH = 0x200000 /* 2M bytes (alias RAM6) */
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}
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/* Define a symbol for the top of each memory region */
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__base_BOARD_FLASH = 0x60000000 ; /* BOARD_FLASH */
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__base_Flash = 0x60000000 ; /* Flash */
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__top_BOARD_FLASH = 0x60000000 + 0x800000 ; /* 8M bytes */
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__top_Flash = 0x60000000 + 0x800000 ; /* 8M bytes */
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__base_SRAM_DTC = 0x20000000 ; /* SRAM_DTC */
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__base_RAM = 0x20000000 ; /* RAM */
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__top_SRAM_DTC = 0x20000000 + 0x20000 ; /* 128K bytes */
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__top_RAM = 0x20000000 + 0x20000 ; /* 128K bytes */
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__base_SRAM_ITC = 0x0 ; /* SRAM_ITC */
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__base_RAM2 = 0x0 ; /* RAM2 */
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__top_SRAM_ITC = 0x0 + 0x20000 ; /* 128K bytes */
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__top_RAM2 = 0x0 + 0x20000 ; /* 128K bytes */
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__base_SRAM_OC2 = 0x20200000 ; /* SRAM_OC2 */
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__base_RAM3 = 0x20200000 ; /* RAM3 */
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__top_SRAM_OC2 = 0x20200000 + 0x80000 ; /* 512K bytes */
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__top_RAM3 = 0x20200000 + 0x80000 ; /* 512K bytes */
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__base_SRAM_OC = 0x20280000 ; /* SRAM_OC */
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__base_RAM4 = 0x20280000 ; /* RAM4 */
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__top_SRAM_OC = 0x20280000 + 0x40000 ; /* 256K bytes */
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__top_RAM4 = 0x20280000 + 0x40000 ; /* 256K bytes */
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__base_BOARD_SDRAM = 0x80000000 ; /* BOARD_SDRAM */
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__base_RAM5 = 0x80000000 ; /* RAM5 */
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__top_BOARD_SDRAM = 0x80000000 + 0x1e00000 ; /* 30M bytes */
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__top_RAM5 = 0x80000000 + 0x1e00000 ; /* 30M bytes */
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__base_NCACHE_REGION = 0x81e00000 ; /* NCACHE_REGION */
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__base_RAM6 = 0x81e00000 ; /* RAM6 */
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__top_NCACHE_REGION = 0x81e00000 + 0x200000 ; /* 2M bytes */
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__top_RAM6 = 0x81e00000 + 0x200000 ; /* 2M bytes */
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