mirror of
https://github.com/cesanta/mongoose.git
synced 2024-12-19 12:08:05 +08:00
422 lines
12 KiB
Plaintext
422 lines
12 KiB
Plaintext
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/*
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* GENERATED FILE - DO NOT EDIT
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* Copyright 2008-2013 Code Red Technologies Ltd,
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* Copyright 2013-2024 NXP
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* Generated linker script file for MIMXRT1062xxxxB
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* Created from linkscript.ldt by FMCreateLinkLibraries
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* Using Freemarker v2.3.30
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* MCUXpresso IDE v11.8.1 [Build 1197] [2023-10-27] on Jan 5, 2024, 8:59:47 PM
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*/
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INCLUDE "rt1060-evk-xpresso-baremetal-builtin_Debug_library.ld"
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INCLUDE "rt1060-evk-xpresso-baremetal-builtin_Debug_memory.ld"
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ENTRY(ResetISR)
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SECTIONS
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{
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/* Image Vector Table and Boot Data for booting from external flash */
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.boot_hdr : ALIGN(4)
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{
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FILL(0xff)
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__boot_hdr_start__ = ABSOLUTE(.) ;
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KEEP(*(.boot_hdr.conf))
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. = 0x1000 ;
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KEEP(*(.boot_hdr.ivt))
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. = 0x1020 ;
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KEEP(*(.boot_hdr.boot_data))
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. = 0x1030 ;
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KEEP(*(.boot_hdr.dcd_data))
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__boot_hdr_end__ = ABSOLUTE(.) ;
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. = 0x2000 ;
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} >BOARD_FLASH
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/* MAIN TEXT SECTION */
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.text : ALIGN(4)
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{
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FILL(0xff)
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__vectors_start__ = ABSOLUTE(.) ;
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KEEP(*(.isr_vector))
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/* Global Section Table */
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. = ALIGN(4) ;
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__section_table_start = .;
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__data_section_table = .;
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LONG(LOADADDR(.data));
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LONG( ADDR(.data));
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LONG( SIZEOF(.data));
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LONG(LOADADDR(.data_RAM2));
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LONG( ADDR(.data_RAM2));
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LONG( SIZEOF(.data_RAM2));
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LONG(LOADADDR(.data_RAM3));
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LONG( ADDR(.data_RAM3));
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LONG( SIZEOF(.data_RAM3));
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LONG(LOADADDR(.data_RAM4));
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LONG( ADDR(.data_RAM4));
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LONG( SIZEOF(.data_RAM4));
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LONG(LOADADDR(.data_RAM5));
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LONG( ADDR(.data_RAM5));
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LONG( SIZEOF(.data_RAM5));
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LONG(LOADADDR(.data_RAM6));
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LONG( ADDR(.data_RAM6));
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LONG( SIZEOF(.data_RAM6));
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__data_section_table_end = .;
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__bss_section_table = .;
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LONG( ADDR(.bss));
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LONG( SIZEOF(.bss));
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LONG( ADDR(.bss_RAM2));
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LONG( SIZEOF(.bss_RAM2));
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LONG( ADDR(.bss_RAM3));
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LONG( SIZEOF(.bss_RAM3));
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LONG( ADDR(.bss_RAM4));
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LONG( SIZEOF(.bss_RAM4));
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LONG( ADDR(.bss_RAM5));
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LONG( SIZEOF(.bss_RAM5));
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LONG( ADDR(.bss_RAM6));
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LONG( SIZEOF(.bss_RAM6));
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__bss_section_table_end = .;
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__section_table_end = . ;
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/* End of Global Section Table */
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*(.after_vectors*)
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*(.text*)
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*(.rodata .rodata.* .constdata .constdata.*)
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. = ALIGN(4);
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} > BOARD_FLASH
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/*
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* for exception handling/unwind - some Newlib functions (in common
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* with C++ and STDC++) use this.
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*/
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.ARM.extab : ALIGN(4)
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{
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*(.ARM.extab* .gnu.linkonce.armextab.*)
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} > BOARD_FLASH
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.ARM.exidx : ALIGN(4)
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{
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__exidx_start = .;
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*(.ARM.exidx* .gnu.linkonce.armexidx.*)
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__exidx_end = .;
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} > BOARD_FLASH
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_etext = .;
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/* DATA section for SRAM_ITC */
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.data_RAM2 : ALIGN(4)
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{
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FILL(0xff)
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PROVIDE(__start_data_RAM2 = .) ;
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PROVIDE(__start_data_SRAM_ITC = .) ;
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*(.ramfunc.$RAM2)
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*(.ramfunc.$SRAM_ITC)
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*(.data.$RAM2)
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*(.data.$SRAM_ITC)
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*(.data.$RAM2.*)
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*(.data.$SRAM_ITC.*)
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. = ALIGN(4) ;
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PROVIDE(__end_data_RAM2 = .) ;
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PROVIDE(__end_data_SRAM_ITC = .) ;
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} > SRAM_ITC AT>BOARD_FLASH
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/* DATA section for SRAM_OC2 */
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.data_RAM3 : ALIGN(4)
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{
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FILL(0xff)
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PROVIDE(__start_data_RAM3 = .) ;
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PROVIDE(__start_data_SRAM_OC2 = .) ;
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*(.ramfunc.$RAM3)
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*(.ramfunc.$SRAM_OC2)
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*(.data.$RAM3)
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*(.data.$SRAM_OC2)
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*(.data.$RAM3.*)
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*(.data.$SRAM_OC2.*)
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. = ALIGN(4) ;
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PROVIDE(__end_data_RAM3 = .) ;
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PROVIDE(__end_data_SRAM_OC2 = .) ;
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} > SRAM_OC2 AT>BOARD_FLASH
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/* DATA section for SRAM_OC */
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.data_RAM4 : ALIGN(4)
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{
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FILL(0xff)
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PROVIDE(__start_data_RAM4 = .) ;
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PROVIDE(__start_data_SRAM_OC = .) ;
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*(.ramfunc.$RAM4)
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*(.ramfunc.$SRAM_OC)
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*(.data.$RAM4)
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*(.data.$SRAM_OC)
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*(.data.$RAM4.*)
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*(.data.$SRAM_OC.*)
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. = ALIGN(4) ;
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PROVIDE(__end_data_RAM4 = .) ;
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PROVIDE(__end_data_SRAM_OC = .) ;
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} > SRAM_OC AT>BOARD_FLASH
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/* DATA section for BOARD_SDRAM */
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.data_RAM5 : ALIGN(4)
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{
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FILL(0xff)
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PROVIDE(__start_data_RAM5 = .) ;
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PROVIDE(__start_data_BOARD_SDRAM = .) ;
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*(.ramfunc.$RAM5)
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*(.ramfunc.$BOARD_SDRAM)
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*(.data.$RAM5)
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*(.data.$BOARD_SDRAM)
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*(.data.$RAM5.*)
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*(.data.$BOARD_SDRAM.*)
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. = ALIGN(4) ;
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PROVIDE(__end_data_RAM5 = .) ;
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PROVIDE(__end_data_BOARD_SDRAM = .) ;
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} > BOARD_SDRAM AT>BOARD_FLASH
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/* DATA section for NCACHE_REGION */
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.data_RAM6 : ALIGN(4)
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{
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FILL(0xff)
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PROVIDE(__start_data_RAM6 = .) ;
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PROVIDE(__start_data_NCACHE_REGION = .) ;
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*(.ramfunc.$RAM6)
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*(.ramfunc.$NCACHE_REGION)
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*(.data.$RAM6)
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*(.data.$NCACHE_REGION)
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*(.data.$RAM6.*)
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*(.data.$NCACHE_REGION.*)
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. = ALIGN(4) ;
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PROVIDE(__end_data_RAM6 = .) ;
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PROVIDE(__end_data_NCACHE_REGION = .) ;
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} > NCACHE_REGION AT>BOARD_FLASH
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/* MAIN DATA SECTION */
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.uninit_RESERVED (NOLOAD) : ALIGN(4)
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{
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_start_uninit_RESERVED = .;
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KEEP(*(.bss.$RESERVED*))
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. = ALIGN(4) ;
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_end_uninit_RESERVED = .;
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} > SRAM_DTC AT> SRAM_DTC
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/* Main DATA section (SRAM_DTC) */
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.data : ALIGN(4)
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{
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FILL(0xff)
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_data = . ;
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PROVIDE(__start_data_RAM = .) ;
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PROVIDE(__start_data_SRAM_DTC = .) ;
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*(vtable)
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*(.ramfunc*)
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KEEP(*(CodeQuickAccess))
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KEEP(*(DataQuickAccess))
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*(RamFunction)
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*(.data*)
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. = ALIGN(4) ;
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_edata = . ;
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PROVIDE(__end_data_RAM = .) ;
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PROVIDE(__end_data_SRAM_DTC = .) ;
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} > SRAM_DTC AT>BOARD_FLASH
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/* BSS section for SRAM_ITC */
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.bss_RAM2 (NOLOAD) : ALIGN(4)
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{
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PROVIDE(__start_bss_RAM2 = .) ;
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PROVIDE(__start_bss_SRAM_ITC = .) ;
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||
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|
*(.bss.$RAM2)
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||
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*(.bss.$SRAM_ITC)
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|
*(.bss.$RAM2.*)
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*(.bss.$SRAM_ITC.*)
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||
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. = ALIGN (. != 0 ? 4 : 1) ; /* avoid empty segment */
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PROVIDE(__end_bss_RAM2 = .) ;
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PROVIDE(__end_bss_SRAM_ITC = .) ;
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||
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} > SRAM_ITC AT> SRAM_ITC
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|
|
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||
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/* BSS section for SRAM_OC2 */
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.bss_RAM3 (NOLOAD) : ALIGN(4)
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{
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PROVIDE(__start_bss_RAM3 = .) ;
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||
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PROVIDE(__start_bss_SRAM_OC2 = .) ;
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||
|
|
*(.bss.$RAM3)
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||
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|
*(.bss.$SRAM_OC2)
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|
*(.bss.$RAM3.*)
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*(.bss.$SRAM_OC2.*)
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|
. = ALIGN (. != 0 ? 4 : 1) ; /* avoid empty segment */
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PROVIDE(__end_bss_RAM3 = .) ;
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PROVIDE(__end_bss_SRAM_OC2 = .) ;
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} > SRAM_OC2 AT> SRAM_OC2
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|
|
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/* BSS section for SRAM_OC */
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.bss_RAM4 (NOLOAD) : ALIGN(4)
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{
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PROVIDE(__start_bss_RAM4 = .) ;
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PROVIDE(__start_bss_SRAM_OC = .) ;
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|
*(.bss.$RAM4)
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|
*(.bss.$SRAM_OC)
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*(.bss.$RAM4.*)
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*(.bss.$SRAM_OC.*)
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. = ALIGN (. != 0 ? 4 : 1) ; /* avoid empty segment */
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PROVIDE(__end_bss_RAM4 = .) ;
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PROVIDE(__end_bss_SRAM_OC = .) ;
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} > SRAM_OC AT> SRAM_OC
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/* BSS section for BOARD_SDRAM */
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.bss_RAM5 (NOLOAD) : ALIGN(4)
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{
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PROVIDE(__start_bss_RAM5 = .) ;
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PROVIDE(__start_bss_BOARD_SDRAM = .) ;
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||
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|
*(.bss.$RAM5)
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|
*(.bss.$BOARD_SDRAM)
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||
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|
*(.bss.$RAM5.*)
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|
*(.bss.$BOARD_SDRAM.*)
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||
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|
. = ALIGN (. != 0 ? 4 : 1) ; /* avoid empty segment */
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PROVIDE(__end_bss_RAM5 = .) ;
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|
PROVIDE(__end_bss_BOARD_SDRAM = .) ;
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||
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|
} > BOARD_SDRAM AT> BOARD_SDRAM
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||
|
|
|
||
|
|
/* BSS section for NCACHE_REGION */
|
||
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|
.bss_RAM6 (NOLOAD) : ALIGN(4)
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||
|
|
{
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||
|
|
PROVIDE(__start_bss_RAM6 = .) ;
|
||
|
|
PROVIDE(__start_bss_NCACHE_REGION = .) ;
|
||
|
|
*(.bss.$RAM6)
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||
|
|
*(.bss.$NCACHE_REGION)
|
||
|
|
*(.bss.$RAM6.*)
|
||
|
|
*(.bss.$NCACHE_REGION.*)
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||
|
|
. = ALIGN (. != 0 ? 4 : 1) ; /* avoid empty segment */
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||
|
|
PROVIDE(__end_bss_RAM6 = .) ;
|
||
|
|
PROVIDE(__end_bss_NCACHE_REGION = .) ;
|
||
|
|
} > NCACHE_REGION AT> NCACHE_REGION
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||
|
|
|
||
|
|
/* MAIN BSS SECTION */
|
||
|
|
.bss (NOLOAD) : ALIGN(4)
|
||
|
|
{
|
||
|
|
_bss = .;
|
||
|
|
PROVIDE(__start_bss_RAM = .) ;
|
||
|
|
PROVIDE(__start_bss_SRAM_DTC = .) ;
|
||
|
|
*(.bss*)
|
||
|
|
*(COMMON)
|
||
|
|
. = ALIGN(4) ;
|
||
|
|
_ebss = .;
|
||
|
|
PROVIDE(__end_bss_RAM = .) ;
|
||
|
|
PROVIDE(__end_bss_SRAM_DTC = .) ;
|
||
|
|
PROVIDE(end = .);
|
||
|
|
} > SRAM_DTC AT> SRAM_DTC
|
||
|
|
|
||
|
|
/* NOINIT section for SRAM_ITC */
|
||
|
|
.noinit_RAM2 (NOLOAD) : ALIGN(4)
|
||
|
|
{
|
||
|
|
PROVIDE(__start_noinit_RAM2 = .) ;
|
||
|
|
PROVIDE(__start_noinit_SRAM_ITC = .) ;
|
||
|
|
*(.noinit.$RAM2)
|
||
|
|
*(.noinit.$SRAM_ITC)
|
||
|
|
*(.noinit.$RAM2.*)
|
||
|
|
*(.noinit.$SRAM_ITC.*)
|
||
|
|
. = ALIGN(4) ;
|
||
|
|
PROVIDE(__end_noinit_RAM2 = .) ;
|
||
|
|
PROVIDE(__end_noinit_SRAM_ITC = .) ;
|
||
|
|
} > SRAM_ITC AT> SRAM_ITC
|
||
|
|
|
||
|
|
/* NOINIT section for SRAM_OC2 */
|
||
|
|
.noinit_RAM3 (NOLOAD) : ALIGN(4)
|
||
|
|
{
|
||
|
|
PROVIDE(__start_noinit_RAM3 = .) ;
|
||
|
|
PROVIDE(__start_noinit_SRAM_OC2 = .) ;
|
||
|
|
*(.noinit.$RAM3)
|
||
|
|
*(.noinit.$SRAM_OC2)
|
||
|
|
*(.noinit.$RAM3.*)
|
||
|
|
*(.noinit.$SRAM_OC2.*)
|
||
|
|
. = ALIGN(4) ;
|
||
|
|
PROVIDE(__end_noinit_RAM3 = .) ;
|
||
|
|
PROVIDE(__end_noinit_SRAM_OC2 = .) ;
|
||
|
|
} > SRAM_OC2 AT> SRAM_OC2
|
||
|
|
|
||
|
|
/* NOINIT section for SRAM_OC */
|
||
|
|
.noinit_RAM4 (NOLOAD) : ALIGN(4)
|
||
|
|
{
|
||
|
|
PROVIDE(__start_noinit_RAM4 = .) ;
|
||
|
|
PROVIDE(__start_noinit_SRAM_OC = .) ;
|
||
|
|
*(.noinit.$RAM4)
|
||
|
|
*(.noinit.$SRAM_OC)
|
||
|
|
*(.noinit.$RAM4.*)
|
||
|
|
*(.noinit.$SRAM_OC.*)
|
||
|
|
. = ALIGN(4) ;
|
||
|
|
PROVIDE(__end_noinit_RAM4 = .) ;
|
||
|
|
PROVIDE(__end_noinit_SRAM_OC = .) ;
|
||
|
|
} > SRAM_OC AT> SRAM_OC
|
||
|
|
|
||
|
|
/* NOINIT section for BOARD_SDRAM */
|
||
|
|
.noinit_RAM5 (NOLOAD) : ALIGN(4)
|
||
|
|
{
|
||
|
|
PROVIDE(__start_noinit_RAM5 = .) ;
|
||
|
|
PROVIDE(__start_noinit_BOARD_SDRAM = .) ;
|
||
|
|
*(.noinit.$RAM5)
|
||
|
|
*(.noinit.$BOARD_SDRAM)
|
||
|
|
*(.noinit.$RAM5.*)
|
||
|
|
*(.noinit.$BOARD_SDRAM.*)
|
||
|
|
. = ALIGN(4) ;
|
||
|
|
PROVIDE(__end_noinit_RAM5 = .) ;
|
||
|
|
PROVIDE(__end_noinit_BOARD_SDRAM = .) ;
|
||
|
|
} > BOARD_SDRAM AT> BOARD_SDRAM
|
||
|
|
|
||
|
|
/* NOINIT section for NCACHE_REGION */
|
||
|
|
.noinit_RAM6 (NOLOAD) : ALIGN(4)
|
||
|
|
{
|
||
|
|
PROVIDE(__start_noinit_RAM6 = .) ;
|
||
|
|
PROVIDE(__start_noinit_NCACHE_REGION = .) ;
|
||
|
|
*(.noinit.$RAM6)
|
||
|
|
*(.noinit.$NCACHE_REGION)
|
||
|
|
*(.noinit.$RAM6.*)
|
||
|
|
*(.noinit.$NCACHE_REGION.*)
|
||
|
|
. = ALIGN(4) ;
|
||
|
|
PROVIDE(__end_noinit_RAM6 = .) ;
|
||
|
|
PROVIDE(__end_noinit_NCACHE_REGION = .) ;
|
||
|
|
} > NCACHE_REGION AT> NCACHE_REGION
|
||
|
|
|
||
|
|
/* DEFAULT NOINIT SECTION */
|
||
|
|
.noinit (NOLOAD): ALIGN(4)
|
||
|
|
{
|
||
|
|
_noinit = .;
|
||
|
|
PROVIDE(__start_noinit_RAM = .) ;
|
||
|
|
PROVIDE(__start_noinit_SRAM_DTC = .) ;
|
||
|
|
*(.noinit*)
|
||
|
|
. = ALIGN(4) ;
|
||
|
|
_end_noinit = .;
|
||
|
|
PROVIDE(__end_noinit_RAM = .) ;
|
||
|
|
PROVIDE(__end_noinit_SRAM_DTC = .) ;
|
||
|
|
} > SRAM_DTC AT> SRAM_DTC
|
||
|
|
|
||
|
|
/* Reserve and place Heap within memory map */
|
||
|
|
_HeapSize = 0x1000;
|
||
|
|
.heap (NOLOAD) : ALIGN(4)
|
||
|
|
{
|
||
|
|
_pvHeapStart = .;
|
||
|
|
. += _HeapSize;
|
||
|
|
. = ALIGN(4);
|
||
|
|
_pvHeapLimit = .;
|
||
|
|
} > SRAM_DTC
|
||
|
|
|
||
|
|
_StackSize = 0x1000;
|
||
|
|
/* Reserve space in memory for Stack */
|
||
|
|
.heap2stackfill (NOLOAD) :
|
||
|
|
{
|
||
|
|
. += _StackSize;
|
||
|
|
} > SRAM_DTC
|
||
|
|
/* Locate actual Stack in memory map */
|
||
|
|
.stack ORIGIN(SRAM_DTC) + LENGTH(SRAM_DTC) - _StackSize - 0 (NOLOAD) : ALIGN(4)
|
||
|
|
{
|
||
|
|
_vStackBase = .;
|
||
|
|
. = ALIGN(4);
|
||
|
|
_vStackTop = . + _StackSize;
|
||
|
|
} > SRAM_DTC
|
||
|
|
|
||
|
|
/* Provide basic symbols giving location and size of main text
|
||
|
|
* block, including initial values of RW data sections. Note that
|
||
|
|
* these will need extending to give a complete picture with
|
||
|
|
* complex images (e.g multiple Flash banks).
|
||
|
|
*/
|
||
|
|
_image_start = LOADADDR(.text);
|
||
|
|
_image_end = LOADADDR(.data) + SIZEOF(.data);
|
||
|
|
_image_size = _image_end - _image_start;
|
||
|
|
}
|