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98 lines
4.0 KiB
C
98 lines
4.0 KiB
C
/* clang-format off */
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/*
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* Copyright (c) 2015, Freescale Semiconductor, Inc.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without modification,
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* are permitted provided that the following conditions are met:
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*
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* o Redistributions of source code must retain the above copyright notice, this list
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* of conditions and the following disclaimer.
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*
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* o Redistributions in binary form must reproduce the above copyright notice, this
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* list of conditions and the following disclaimer in the documentation and/or
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* other materials provided with the distribution.
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*
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* o Neither the name of Freescale Semiconductor, Inc. nor the names of its
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* contributors may be used to endorse or promote products derived from this
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* software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
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* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
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* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
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* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#include "fsl_device_registers.h"
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#include "fsl_common.h"
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#include "fsl_port.h"
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#include "pin_mux.h"
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/*******************************************************************************
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* Code
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******************************************************************************/
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void BOARD_InitPins(void)
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{
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port_pin_config_t configENET = {0};
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/* Initialize UART0 pins below */
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/* Ungate the port clock */
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/* Ungate the port clock */
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CLOCK_EnableClock(kCLOCK_PortB);
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/* Affects PORTB_PCR16 register */
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PORT_SetPinMux(PORTB, 16u, kPORT_MuxAlt3);
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/* Affects PORTB_PCR17 register */
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PORT_SetPinMux(PORTB, 17u, kPORT_MuxAlt3);
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CLOCK_EnableClock(kCLOCK_PortC);
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/* Affects PORTC_PCR16 register */
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PORT_SetPinMux(PORTC, 16u, kPORT_MuxAlt4);
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/* Affects PORTC_PCR17 register */
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PORT_SetPinMux(PORTC, 17u, kPORT_MuxAlt4);
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/* Affects PORTC_PCR18 register */
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PORT_SetPinMux(PORTC, 18u, kPORT_MuxAlt4);
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/* Affects PORTC_PCR19 register */
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PORT_SetPinMux(PORTC, 19u, kPORT_MuxAlt4);
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/* Affects PORTB_PCR1 register */
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PORT_SetPinMux(PORTB, 1u, kPORT_MuxAlt4);
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configENET.openDrainEnable = kPORT_OpenDrainEnable;
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configENET.mux = kPORT_MuxAlt4;
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configENET.pullSelect = kPORT_PullUp;
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/* Ungate the port clock */
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CLOCK_EnableClock(kCLOCK_PortA);
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/* Affects PORTB_PCR0 register */
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PORT_SetPinConfig(PORTB, 0u, &configENET);
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/* Affects PORTA_PCR13 register */
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PORT_SetPinMux(PORTA, 13u, kPORT_MuxAlt4);
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/* Affects PORTA_PCR12 register */
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PORT_SetPinMux(PORTA, 12u, kPORT_MuxAlt4);
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/* Affects PORTA_PCR14 register */
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PORT_SetPinMux(PORTA, 14u, kPORT_MuxAlt4);
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/* Affects PORTA_PCR5 register */
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PORT_SetPinMux(PORTA, 5u, kPORT_MuxAlt4);
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/* Affects PORTA_PCR16 register */
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PORT_SetPinMux(PORTA, 16u, kPORT_MuxAlt4);
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/* Affects PORTA_PCR17 register */
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PORT_SetPinMux(PORTA, 17u, kPORT_MuxAlt4);
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/* Affects PORTA_PCR15 register */
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PORT_SetPinMux(PORTA, 15u, kPORT_MuxAlt4);
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/* Affects PORTA_PCR28 register */
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PORT_SetPinMux(PORTA, 28u, kPORT_MuxAlt4);
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/* Enable SW port clock */
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CLOCK_EnableClock(kCLOCK_PortA);
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/* Affects PORTA_PCR4 register */
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port_pin_config_t config = {0};
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config.pullSelect = kPORT_PullUp;
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config.mux = kPORT_MuxAsGpio;
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PORT_SetPinConfig(PORTA, 4U, &config);
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}
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