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fix atomic operations on ppc64
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@ -17,6 +17,58 @@
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* The "=&b" means that no input registers can be used.
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*/
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#if (NGX_PTR_SIZE == 8)
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static ngx_inline ngx_atomic_uint_t
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ngx_atomic_cmp_set(ngx_atomic_t *lock, ngx_atomic_uint_t old,
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ngx_atomic_uint_t set)
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{
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ngx_atomic_uint_t res, temp;
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__asm__ volatile (
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" li %0, 0 \n" /* preset "0" to "res" */
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" ldarx %1, 0, %2 \n" /* load from [lock] into "temp" */
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/* and store reservation */
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" cmpd %1, %3 \n" /* compare "temp" and "old" */
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" bne- 1f \n" /* not equal */
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" stdcx. %4, 0, %2 \n" /* store "set" into [lock] if reservation */
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/* is not cleared */
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" bne- 1f \n" /* the reservation was cleared */
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" li %0, 1 \n" /* set "1" to "res" */
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"1: \n"
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: "=&b" (res), "=&b" (temp)
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: "b" (lock), "b" (old), "b" (set)
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: "cc", "memory");
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return res;
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}
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static ngx_inline ngx_atomic_int_t
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ngx_atomic_fetch_add(ngx_atomic_t *value, ngx_atomic_int_t add)
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{
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ngx_atomic_uint_t res, temp;
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__asm__ volatile (
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"1: ldarx %0, 0, %2 \n" /* load from [value] into "res" */
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/* and store reservation */
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" add %1, %0, %3 \n" /* "res" + "add" store in "temp" */
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" stdcx. %1, 0, %2 \n" /* store "temp" into [value] if reservation */
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/* is not cleared */
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" bne- 1b \n" /* try again if reservation was cleared */
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: "=&b" (res), "=&b" (temp)
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: "b" (value), "b" (add)
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: "cc", "memory");
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return res;
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}
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#else
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static ngx_inline ngx_atomic_uint_t
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ngx_atomic_cmp_set(ngx_atomic_t *lock, ngx_atomic_uint_t old,
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ngx_atomic_uint_t set)
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@ -65,6 +117,8 @@ ngx_atomic_fetch_add(ngx_atomic_t *value, ngx_atomic_int_t add)
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return res;
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}
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#endif
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#if (NGX_SMP)
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#define ngx_memory_barrier() __asm__ volatile ("sync\n" ::: "memory")
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