2018-02-06 20:02:51 +08:00
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// This file is part of OpenCV project.
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// It is subject to the license terms in the LICENSE file found in the top-level directory
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// of this distribution and at http://opencv.org/license.html
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2015-12-03 19:43:37 +08:00
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#include "precomp.hpp"
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namespace cv { namespace hal {
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2019-02-22 17:35:32 +08:00
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CV_CPU_OPTIMIZATION_NAMESPACE_BEGIN
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void split8u(const uchar* src, uchar** dst, int len, int cn);
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void split16u(const ushort* src, ushort** dst, int len, int cn);
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void split32s(const int* src, int** dst, int len, int cn);
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void split64s(const int64* src, int64** dst, int len, int cn);
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#ifndef CV_CPU_OPTIMIZATION_DECLARATIONS_ONLY
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2015-12-03 19:43:37 +08:00
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Merge pull request #23980 from hanliutong:rewrite-core
Rewrite Universal Intrinsic code by using new API: Core module. #23980
The goal of this PR is to match and modify all SIMD code blocks guarded by `CV_SIMD` macro in the `opencv/modules/core` folder and rewrite them by using the new Universal Intrinsic API.
The patch is almost auto-generated by using the [rewriter](https://github.com/hanliutong/rewriter), related PR #23885.
Most of the files have been rewritten, but I marked this PR as draft because, the `CV_SIMD` macro also exists in the following files, and the reasons why they are not rewrited are:
1. ~~code design for fixed-size SIMD (v_int16x8, v_float32x4, etc.), need to manually rewrite.~~ Rewrited
- ./modules/core/src/stat.simd.hpp
- ./modules/core/src/matrix_transform.cpp
- ./modules/core/src/matmul.simd.hpp
2. Vector types are wrapped in other class/struct, that are not supported by the compiler in variable-length backends. Can not be rewrited directly.
- ./modules/core/src/mathfuncs_core.simd.hpp
```cpp
struct v_atan_f32
{
explicit v_atan_f32(const float& scale)
{
...
}
v_float32 compute(const v_float32& y, const v_float32& x)
{
...
}
...
v_float32 val90; // sizeless type can not used in a class
v_float32 val180;
v_float32 val360;
v_float32 s;
};
```
3. The API interface does not support/does not match
- ./modules/core/src/norm.cpp
Use `v_popcount`, ~~waiting for #23966~~ Fixed
- ./modules/core/src/has_non_zero.simd.hpp
Use illegal Universal Intrinsic API: For float type, there is no logical operation `|`. Further discussion needed
```cpp
/** @brief Bitwise OR
Only for integer types. */
template<typename _Tp, int n> CV_INLINE v_reg<_Tp, n> operator|(const v_reg<_Tp, n>& a, const v_reg<_Tp, n>& b);
template<typename _Tp, int n> CV_INLINE v_reg<_Tp, n>& operator|=(v_reg<_Tp, n>& a, const v_reg<_Tp, n>& b);
```
```cpp
#if CV_SIMD
typedef v_float32 v_type;
const v_type v_zero = vx_setzero_f32();
constexpr const int unrollCount = 8;
int step = v_type::nlanes * unrollCount;
int len0 = len & -step;
const float* srcSimdEnd = src+len0;
int countSIMD = static_cast<int>((srcSimdEnd-src)/step);
while(!res && countSIMD--)
{
v_type v0 = vx_load(src);
src += v_type::nlanes;
v_type v1 = vx_load(src);
src += v_type::nlanes;
....
src += v_type::nlanes;
v0 |= v1; //Illegal ?
....
//res = v_check_any(((v0 | v4) != v_zero));//beware : (NaN != 0) returns "false" since != is mapped to _CMP_NEQ_OQ and not _CMP_NEQ_UQ
res = !v_check_all(((v0 | v4) == v_zero));
}
v_cleanup();
#endif
```
### Pull Request Readiness Checklist
See details at https://github.com/opencv/opencv/wiki/How_to_contribute#making-a-good-pull-request
- [ ] I agree to contribute to the project under Apache 2 License.
- [ ] To the best of my knowledge, the proposed patch is not based on a code under GPL or another license that is incompatible with OpenCV
- [ ] The PR is proposed to the proper branch
- [ ] There is a reference to the original bug report and related work
- [ ] There is accuracy test, performance test and test data in opencv_extra repository, if applicable
Patch to opencv_extra has the same branch name.
- [ ] The feature is well documented and sample code can be built with the project CMake
2023-08-11 13:33:33 +08:00
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#if (CV_SIMD || CV_SIMD_SCALABLE)
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2018-07-26 17:04:28 +08:00
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// see the comments for vecmerge_ in merge.cpp
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2018-07-24 22:27:56 +08:00
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template<typename T, typename VecT> static void
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vecsplit_( const T* src, T** dst, int len, int cn )
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{
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Merge pull request #23980 from hanliutong:rewrite-core
Rewrite Universal Intrinsic code by using new API: Core module. #23980
The goal of this PR is to match and modify all SIMD code blocks guarded by `CV_SIMD` macro in the `opencv/modules/core` folder and rewrite them by using the new Universal Intrinsic API.
The patch is almost auto-generated by using the [rewriter](https://github.com/hanliutong/rewriter), related PR #23885.
Most of the files have been rewritten, but I marked this PR as draft because, the `CV_SIMD` macro also exists in the following files, and the reasons why they are not rewrited are:
1. ~~code design for fixed-size SIMD (v_int16x8, v_float32x4, etc.), need to manually rewrite.~~ Rewrited
- ./modules/core/src/stat.simd.hpp
- ./modules/core/src/matrix_transform.cpp
- ./modules/core/src/matmul.simd.hpp
2. Vector types are wrapped in other class/struct, that are not supported by the compiler in variable-length backends. Can not be rewrited directly.
- ./modules/core/src/mathfuncs_core.simd.hpp
```cpp
struct v_atan_f32
{
explicit v_atan_f32(const float& scale)
{
...
}
v_float32 compute(const v_float32& y, const v_float32& x)
{
...
}
...
v_float32 val90; // sizeless type can not used in a class
v_float32 val180;
v_float32 val360;
v_float32 s;
};
```
3. The API interface does not support/does not match
- ./modules/core/src/norm.cpp
Use `v_popcount`, ~~waiting for #23966~~ Fixed
- ./modules/core/src/has_non_zero.simd.hpp
Use illegal Universal Intrinsic API: For float type, there is no logical operation `|`. Further discussion needed
```cpp
/** @brief Bitwise OR
Only for integer types. */
template<typename _Tp, int n> CV_INLINE v_reg<_Tp, n> operator|(const v_reg<_Tp, n>& a, const v_reg<_Tp, n>& b);
template<typename _Tp, int n> CV_INLINE v_reg<_Tp, n>& operator|=(v_reg<_Tp, n>& a, const v_reg<_Tp, n>& b);
```
```cpp
#if CV_SIMD
typedef v_float32 v_type;
const v_type v_zero = vx_setzero_f32();
constexpr const int unrollCount = 8;
int step = v_type::nlanes * unrollCount;
int len0 = len & -step;
const float* srcSimdEnd = src+len0;
int countSIMD = static_cast<int>((srcSimdEnd-src)/step);
while(!res && countSIMD--)
{
v_type v0 = vx_load(src);
src += v_type::nlanes;
v_type v1 = vx_load(src);
src += v_type::nlanes;
....
src += v_type::nlanes;
v0 |= v1; //Illegal ?
....
//res = v_check_any(((v0 | v4) != v_zero));//beware : (NaN != 0) returns "false" since != is mapped to _CMP_NEQ_OQ and not _CMP_NEQ_UQ
res = !v_check_all(((v0 | v4) == v_zero));
}
v_cleanup();
#endif
```
### Pull Request Readiness Checklist
See details at https://github.com/opencv/opencv/wiki/How_to_contribute#making-a-good-pull-request
- [ ] I agree to contribute to the project under Apache 2 License.
- [ ] To the best of my knowledge, the proposed patch is not based on a code under GPL or another license that is incompatible with OpenCV
- [ ] The PR is proposed to the proper branch
- [ ] There is a reference to the original bug report and related work
- [ ] There is accuracy test, performance test and test data in opencv_extra repository, if applicable
Patch to opencv_extra has the same branch name.
- [ ] The feature is well documented and sample code can be built with the project CMake
2023-08-11 13:33:33 +08:00
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const int VECSZ = VTraits<VecT>::vlanes();
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2018-07-26 17:04:28 +08:00
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int i, i0 = 0;
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2018-07-24 22:27:56 +08:00
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T* dst0 = dst[0];
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T* dst1 = dst[1];
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2015-12-03 19:43:37 +08:00
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2018-07-26 17:04:28 +08:00
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int r0 = (int)((size_t)(void*)dst0 % (VECSZ*sizeof(T)));
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int r1 = (int)((size_t)(void*)dst1 % (VECSZ*sizeof(T)));
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int r2 = cn > 2 ? (int)((size_t)(void*)dst[2] % (VECSZ*sizeof(T))) : r0;
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int r3 = cn > 3 ? (int)((size_t)(void*)dst[3] % (VECSZ*sizeof(T))) : r0;
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hal::StoreMode mode = hal::STORE_ALIGNED_NOCACHE;
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if( (r0|r1|r2|r3) != 0 )
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{
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mode = hal::STORE_UNALIGNED;
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2018-08-07 23:11:05 +08:00
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if( r0 == r1 && r0 == r2 && r0 == r3 && r0 % sizeof(T) == 0 && len > VECSZ*2 )
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i0 = VECSZ - (r0 / sizeof(T));
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2018-07-26 17:04:28 +08:00
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}
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2018-07-24 22:27:56 +08:00
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if( cn == 2 )
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{
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for( i = 0; i < len; i += VECSZ )
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{
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2018-07-26 17:04:28 +08:00
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if( i > len - VECSZ )
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{
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i = len - VECSZ;
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mode = hal::STORE_UNALIGNED;
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}
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2018-07-24 22:27:56 +08:00
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VecT a, b;
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v_load_deinterleave(src + i*cn, a, b);
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2018-07-26 17:04:28 +08:00
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v_store(dst0 + i, a, mode);
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v_store(dst1 + i, b, mode);
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if( i < i0 )
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{
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i = i0 - VECSZ;
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mode = hal::STORE_ALIGNED_NOCACHE;
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}
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2018-07-24 22:27:56 +08:00
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}
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2015-12-03 19:43:37 +08:00
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}
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2018-07-24 22:27:56 +08:00
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else if( cn == 3 )
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{
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T* dst2 = dst[2];
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for( i = 0; i < len; i += VECSZ )
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{
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2018-07-26 17:04:28 +08:00
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if( i > len - VECSZ )
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{
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i = len - VECSZ;
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mode = hal::STORE_UNALIGNED;
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}
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2018-07-24 22:27:56 +08:00
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VecT a, b, c;
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v_load_deinterleave(src + i*cn, a, b, c);
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2018-07-26 17:04:28 +08:00
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v_store(dst0 + i, a, mode);
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v_store(dst1 + i, b, mode);
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v_store(dst2 + i, c, mode);
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if( i < i0 )
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{
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i = i0 - VECSZ;
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mode = hal::STORE_ALIGNED_NOCACHE;
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}
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2018-07-24 22:27:56 +08:00
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}
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2015-12-03 19:43:37 +08:00
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}
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2018-07-24 22:27:56 +08:00
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else
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{
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CV_Assert( cn == 4 );
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T* dst2 = dst[2];
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T* dst3 = dst[3];
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for( i = 0; i < len; i += VECSZ )
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{
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2018-07-26 17:04:28 +08:00
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if( i > len - VECSZ )
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{
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i = len - VECSZ;
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mode = hal::STORE_UNALIGNED;
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}
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2018-07-24 22:27:56 +08:00
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VecT a, b, c, d;
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v_load_deinterleave(src + i*cn, a, b, c, d);
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2018-07-26 17:04:28 +08:00
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v_store(dst0 + i, a, mode);
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v_store(dst1 + i, b, mode);
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v_store(dst2 + i, c, mode);
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v_store(dst3 + i, d, mode);
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if( i < i0 )
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{
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i = i0 - VECSZ;
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mode = hal::STORE_ALIGNED_NOCACHE;
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}
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2018-07-24 22:27:56 +08:00
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}
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2015-12-03 19:43:37 +08:00
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}
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2018-07-24 22:27:56 +08:00
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vx_cleanup();
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2015-12-03 19:43:37 +08:00
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}
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#endif
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template<typename T> static void
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split_( const T* src, T** dst, int len, int cn )
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{
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int k = cn % 4 ? cn % 4 : 4;
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int i, j;
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if( k == 1 )
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{
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T* dst0 = dst[0];
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if(cn == 1)
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{
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memcpy(dst0, src, len * sizeof(T));
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}
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else
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{
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for( i = 0, j = 0 ; i < len; i++, j += cn )
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dst0[i] = src[j];
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}
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}
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else if( k == 2 )
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{
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T *dst0 = dst[0], *dst1 = dst[1];
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i = j = 0;
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for( ; i < len; i++, j += cn )
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{
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dst0[i] = src[j];
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dst1[i] = src[j+1];
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}
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}
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else if( k == 3 )
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{
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T *dst0 = dst[0], *dst1 = dst[1], *dst2 = dst[2];
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i = j = 0;
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for( ; i < len; i++, j += cn )
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{
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dst0[i] = src[j];
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dst1[i] = src[j+1];
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dst2[i] = src[j+2];
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}
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}
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else
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{
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T *dst0 = dst[0], *dst1 = dst[1], *dst2 = dst[2], *dst3 = dst[3];
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i = j = 0;
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for( ; i < len; i++, j += cn )
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{
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dst0[i] = src[j]; dst1[i] = src[j+1];
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dst2[i] = src[j+2]; dst3[i] = src[j+3];
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}
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}
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for( ; k < cn; k += 4 )
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{
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T *dst0 = dst[k], *dst1 = dst[k+1], *dst2 = dst[k+2], *dst3 = dst[k+3];
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for( i = 0, j = k; i < len; i++, j += cn )
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{
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dst0[i] = src[j]; dst1[i] = src[j+1];
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dst2[i] = src[j+2]; dst3[i] = src[j+3];
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}
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}
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}
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void split8u(const uchar* src, uchar** dst, int len, int cn )
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{
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2019-02-22 17:35:32 +08:00
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CV_INSTRUMENT_REGION();
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Merge pull request #23980 from hanliutong:rewrite-core
Rewrite Universal Intrinsic code by using new API: Core module. #23980
The goal of this PR is to match and modify all SIMD code blocks guarded by `CV_SIMD` macro in the `opencv/modules/core` folder and rewrite them by using the new Universal Intrinsic API.
The patch is almost auto-generated by using the [rewriter](https://github.com/hanliutong/rewriter), related PR #23885.
Most of the files have been rewritten, but I marked this PR as draft because, the `CV_SIMD` macro also exists in the following files, and the reasons why they are not rewrited are:
1. ~~code design for fixed-size SIMD (v_int16x8, v_float32x4, etc.), need to manually rewrite.~~ Rewrited
- ./modules/core/src/stat.simd.hpp
- ./modules/core/src/matrix_transform.cpp
- ./modules/core/src/matmul.simd.hpp
2. Vector types are wrapped in other class/struct, that are not supported by the compiler in variable-length backends. Can not be rewrited directly.
- ./modules/core/src/mathfuncs_core.simd.hpp
```cpp
struct v_atan_f32
{
explicit v_atan_f32(const float& scale)
{
...
}
v_float32 compute(const v_float32& y, const v_float32& x)
{
...
}
...
v_float32 val90; // sizeless type can not used in a class
v_float32 val180;
v_float32 val360;
v_float32 s;
};
```
3. The API interface does not support/does not match
- ./modules/core/src/norm.cpp
Use `v_popcount`, ~~waiting for #23966~~ Fixed
- ./modules/core/src/has_non_zero.simd.hpp
Use illegal Universal Intrinsic API: For float type, there is no logical operation `|`. Further discussion needed
```cpp
/** @brief Bitwise OR
Only for integer types. */
template<typename _Tp, int n> CV_INLINE v_reg<_Tp, n> operator|(const v_reg<_Tp, n>& a, const v_reg<_Tp, n>& b);
template<typename _Tp, int n> CV_INLINE v_reg<_Tp, n>& operator|=(v_reg<_Tp, n>& a, const v_reg<_Tp, n>& b);
```
```cpp
#if CV_SIMD
typedef v_float32 v_type;
const v_type v_zero = vx_setzero_f32();
constexpr const int unrollCount = 8;
int step = v_type::nlanes * unrollCount;
int len0 = len & -step;
const float* srcSimdEnd = src+len0;
int countSIMD = static_cast<int>((srcSimdEnd-src)/step);
while(!res && countSIMD--)
{
v_type v0 = vx_load(src);
src += v_type::nlanes;
v_type v1 = vx_load(src);
src += v_type::nlanes;
....
src += v_type::nlanes;
v0 |= v1; //Illegal ?
....
//res = v_check_any(((v0 | v4) != v_zero));//beware : (NaN != 0) returns "false" since != is mapped to _CMP_NEQ_OQ and not _CMP_NEQ_UQ
res = !v_check_all(((v0 | v4) == v_zero));
}
v_cleanup();
#endif
```
### Pull Request Readiness Checklist
See details at https://github.com/opencv/opencv/wiki/How_to_contribute#making-a-good-pull-request
- [ ] I agree to contribute to the project under Apache 2 License.
- [ ] To the best of my knowledge, the proposed patch is not based on a code under GPL or another license that is incompatible with OpenCV
- [ ] The PR is proposed to the proper branch
- [ ] There is a reference to the original bug report and related work
- [ ] There is accuracy test, performance test and test data in opencv_extra repository, if applicable
Patch to opencv_extra has the same branch name.
- [ ] The feature is well documented and sample code can be built with the project CMake
2023-08-11 13:33:33 +08:00
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#if (CV_SIMD || CV_SIMD_SCALABLE)
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if( len >= VTraits<v_uint8>::vlanes() && 2 <= cn && cn <= 4 )
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2018-07-24 22:27:56 +08:00
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vecsplit_<uchar, v_uint8>(src, dst, len, cn);
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else
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|
|
|
#endif
|
|
|
|
split_(src, dst, len, cn);
|
2015-12-03 19:43:37 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
void split16u(const ushort* src, ushort** dst, int len, int cn )
|
|
|
|
{
|
2019-02-22 17:35:32 +08:00
|
|
|
CV_INSTRUMENT_REGION();
|
Merge pull request #23980 from hanliutong:rewrite-core
Rewrite Universal Intrinsic code by using new API: Core module. #23980
The goal of this PR is to match and modify all SIMD code blocks guarded by `CV_SIMD` macro in the `opencv/modules/core` folder and rewrite them by using the new Universal Intrinsic API.
The patch is almost auto-generated by using the [rewriter](https://github.com/hanliutong/rewriter), related PR #23885.
Most of the files have been rewritten, but I marked this PR as draft because, the `CV_SIMD` macro also exists in the following files, and the reasons why they are not rewrited are:
1. ~~code design for fixed-size SIMD (v_int16x8, v_float32x4, etc.), need to manually rewrite.~~ Rewrited
- ./modules/core/src/stat.simd.hpp
- ./modules/core/src/matrix_transform.cpp
- ./modules/core/src/matmul.simd.hpp
2. Vector types are wrapped in other class/struct, that are not supported by the compiler in variable-length backends. Can not be rewrited directly.
- ./modules/core/src/mathfuncs_core.simd.hpp
```cpp
struct v_atan_f32
{
explicit v_atan_f32(const float& scale)
{
...
}
v_float32 compute(const v_float32& y, const v_float32& x)
{
...
}
...
v_float32 val90; // sizeless type can not used in a class
v_float32 val180;
v_float32 val360;
v_float32 s;
};
```
3. The API interface does not support/does not match
- ./modules/core/src/norm.cpp
Use `v_popcount`, ~~waiting for #23966~~ Fixed
- ./modules/core/src/has_non_zero.simd.hpp
Use illegal Universal Intrinsic API: For float type, there is no logical operation `|`. Further discussion needed
```cpp
/** @brief Bitwise OR
Only for integer types. */
template<typename _Tp, int n> CV_INLINE v_reg<_Tp, n> operator|(const v_reg<_Tp, n>& a, const v_reg<_Tp, n>& b);
template<typename _Tp, int n> CV_INLINE v_reg<_Tp, n>& operator|=(v_reg<_Tp, n>& a, const v_reg<_Tp, n>& b);
```
```cpp
#if CV_SIMD
typedef v_float32 v_type;
const v_type v_zero = vx_setzero_f32();
constexpr const int unrollCount = 8;
int step = v_type::nlanes * unrollCount;
int len0 = len & -step;
const float* srcSimdEnd = src+len0;
int countSIMD = static_cast<int>((srcSimdEnd-src)/step);
while(!res && countSIMD--)
{
v_type v0 = vx_load(src);
src += v_type::nlanes;
v_type v1 = vx_load(src);
src += v_type::nlanes;
....
src += v_type::nlanes;
v0 |= v1; //Illegal ?
....
//res = v_check_any(((v0 | v4) != v_zero));//beware : (NaN != 0) returns "false" since != is mapped to _CMP_NEQ_OQ and not _CMP_NEQ_UQ
res = !v_check_all(((v0 | v4) == v_zero));
}
v_cleanup();
#endif
```
### Pull Request Readiness Checklist
See details at https://github.com/opencv/opencv/wiki/How_to_contribute#making-a-good-pull-request
- [ ] I agree to contribute to the project under Apache 2 License.
- [ ] To the best of my knowledge, the proposed patch is not based on a code under GPL or another license that is incompatible with OpenCV
- [ ] The PR is proposed to the proper branch
- [ ] There is a reference to the original bug report and related work
- [ ] There is accuracy test, performance test and test data in opencv_extra repository, if applicable
Patch to opencv_extra has the same branch name.
- [ ] The feature is well documented and sample code can be built with the project CMake
2023-08-11 13:33:33 +08:00
|
|
|
#if (CV_SIMD || CV_SIMD_SCALABLE)
|
|
|
|
if( len >= VTraits<v_uint16>::vlanes() && 2 <= cn && cn <= 4 )
|
2018-07-24 22:27:56 +08:00
|
|
|
vecsplit_<ushort, v_uint16>(src, dst, len, cn);
|
|
|
|
else
|
|
|
|
#endif
|
|
|
|
split_(src, dst, len, cn);
|
2015-12-03 19:43:37 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
void split32s(const int* src, int** dst, int len, int cn )
|
|
|
|
{
|
2019-02-22 17:35:32 +08:00
|
|
|
CV_INSTRUMENT_REGION();
|
Merge pull request #23980 from hanliutong:rewrite-core
Rewrite Universal Intrinsic code by using new API: Core module. #23980
The goal of this PR is to match and modify all SIMD code blocks guarded by `CV_SIMD` macro in the `opencv/modules/core` folder and rewrite them by using the new Universal Intrinsic API.
The patch is almost auto-generated by using the [rewriter](https://github.com/hanliutong/rewriter), related PR #23885.
Most of the files have been rewritten, but I marked this PR as draft because, the `CV_SIMD` macro also exists in the following files, and the reasons why they are not rewrited are:
1. ~~code design for fixed-size SIMD (v_int16x8, v_float32x4, etc.), need to manually rewrite.~~ Rewrited
- ./modules/core/src/stat.simd.hpp
- ./modules/core/src/matrix_transform.cpp
- ./modules/core/src/matmul.simd.hpp
2. Vector types are wrapped in other class/struct, that are not supported by the compiler in variable-length backends. Can not be rewrited directly.
- ./modules/core/src/mathfuncs_core.simd.hpp
```cpp
struct v_atan_f32
{
explicit v_atan_f32(const float& scale)
{
...
}
v_float32 compute(const v_float32& y, const v_float32& x)
{
...
}
...
v_float32 val90; // sizeless type can not used in a class
v_float32 val180;
v_float32 val360;
v_float32 s;
};
```
3. The API interface does not support/does not match
- ./modules/core/src/norm.cpp
Use `v_popcount`, ~~waiting for #23966~~ Fixed
- ./modules/core/src/has_non_zero.simd.hpp
Use illegal Universal Intrinsic API: For float type, there is no logical operation `|`. Further discussion needed
```cpp
/** @brief Bitwise OR
Only for integer types. */
template<typename _Tp, int n> CV_INLINE v_reg<_Tp, n> operator|(const v_reg<_Tp, n>& a, const v_reg<_Tp, n>& b);
template<typename _Tp, int n> CV_INLINE v_reg<_Tp, n>& operator|=(v_reg<_Tp, n>& a, const v_reg<_Tp, n>& b);
```
```cpp
#if CV_SIMD
typedef v_float32 v_type;
const v_type v_zero = vx_setzero_f32();
constexpr const int unrollCount = 8;
int step = v_type::nlanes * unrollCount;
int len0 = len & -step;
const float* srcSimdEnd = src+len0;
int countSIMD = static_cast<int>((srcSimdEnd-src)/step);
while(!res && countSIMD--)
{
v_type v0 = vx_load(src);
src += v_type::nlanes;
v_type v1 = vx_load(src);
src += v_type::nlanes;
....
src += v_type::nlanes;
v0 |= v1; //Illegal ?
....
//res = v_check_any(((v0 | v4) != v_zero));//beware : (NaN != 0) returns "false" since != is mapped to _CMP_NEQ_OQ and not _CMP_NEQ_UQ
res = !v_check_all(((v0 | v4) == v_zero));
}
v_cleanup();
#endif
```
### Pull Request Readiness Checklist
See details at https://github.com/opencv/opencv/wiki/How_to_contribute#making-a-good-pull-request
- [ ] I agree to contribute to the project under Apache 2 License.
- [ ] To the best of my knowledge, the proposed patch is not based on a code under GPL or another license that is incompatible with OpenCV
- [ ] The PR is proposed to the proper branch
- [ ] There is a reference to the original bug report and related work
- [ ] There is accuracy test, performance test and test data in opencv_extra repository, if applicable
Patch to opencv_extra has the same branch name.
- [ ] The feature is well documented and sample code can be built with the project CMake
2023-08-11 13:33:33 +08:00
|
|
|
#if (CV_SIMD || CV_SIMD_SCALABLE)
|
|
|
|
if( len >= VTraits<v_uint32>::vlanes() && 2 <= cn && cn <= 4 )
|
2018-07-24 22:27:56 +08:00
|
|
|
vecsplit_<int, v_int32>(src, dst, len, cn);
|
|
|
|
else
|
|
|
|
#endif
|
|
|
|
split_(src, dst, len, cn);
|
2015-12-03 19:43:37 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
void split64s(const int64* src, int64** dst, int len, int cn )
|
|
|
|
{
|
2019-02-22 17:35:32 +08:00
|
|
|
CV_INSTRUMENT_REGION();
|
Merge pull request #23980 from hanliutong:rewrite-core
Rewrite Universal Intrinsic code by using new API: Core module. #23980
The goal of this PR is to match and modify all SIMD code blocks guarded by `CV_SIMD` macro in the `opencv/modules/core` folder and rewrite them by using the new Universal Intrinsic API.
The patch is almost auto-generated by using the [rewriter](https://github.com/hanliutong/rewriter), related PR #23885.
Most of the files have been rewritten, but I marked this PR as draft because, the `CV_SIMD` macro also exists in the following files, and the reasons why they are not rewrited are:
1. ~~code design for fixed-size SIMD (v_int16x8, v_float32x4, etc.), need to manually rewrite.~~ Rewrited
- ./modules/core/src/stat.simd.hpp
- ./modules/core/src/matrix_transform.cpp
- ./modules/core/src/matmul.simd.hpp
2. Vector types are wrapped in other class/struct, that are not supported by the compiler in variable-length backends. Can not be rewrited directly.
- ./modules/core/src/mathfuncs_core.simd.hpp
```cpp
struct v_atan_f32
{
explicit v_atan_f32(const float& scale)
{
...
}
v_float32 compute(const v_float32& y, const v_float32& x)
{
...
}
...
v_float32 val90; // sizeless type can not used in a class
v_float32 val180;
v_float32 val360;
v_float32 s;
};
```
3. The API interface does not support/does not match
- ./modules/core/src/norm.cpp
Use `v_popcount`, ~~waiting for #23966~~ Fixed
- ./modules/core/src/has_non_zero.simd.hpp
Use illegal Universal Intrinsic API: For float type, there is no logical operation `|`. Further discussion needed
```cpp
/** @brief Bitwise OR
Only for integer types. */
template<typename _Tp, int n> CV_INLINE v_reg<_Tp, n> operator|(const v_reg<_Tp, n>& a, const v_reg<_Tp, n>& b);
template<typename _Tp, int n> CV_INLINE v_reg<_Tp, n>& operator|=(v_reg<_Tp, n>& a, const v_reg<_Tp, n>& b);
```
```cpp
#if CV_SIMD
typedef v_float32 v_type;
const v_type v_zero = vx_setzero_f32();
constexpr const int unrollCount = 8;
int step = v_type::nlanes * unrollCount;
int len0 = len & -step;
const float* srcSimdEnd = src+len0;
int countSIMD = static_cast<int>((srcSimdEnd-src)/step);
while(!res && countSIMD--)
{
v_type v0 = vx_load(src);
src += v_type::nlanes;
v_type v1 = vx_load(src);
src += v_type::nlanes;
....
src += v_type::nlanes;
v0 |= v1; //Illegal ?
....
//res = v_check_any(((v0 | v4) != v_zero));//beware : (NaN != 0) returns "false" since != is mapped to _CMP_NEQ_OQ and not _CMP_NEQ_UQ
res = !v_check_all(((v0 | v4) == v_zero));
}
v_cleanup();
#endif
```
### Pull Request Readiness Checklist
See details at https://github.com/opencv/opencv/wiki/How_to_contribute#making-a-good-pull-request
- [ ] I agree to contribute to the project under Apache 2 License.
- [ ] To the best of my knowledge, the proposed patch is not based on a code under GPL or another license that is incompatible with OpenCV
- [ ] The PR is proposed to the proper branch
- [ ] There is a reference to the original bug report and related work
- [ ] There is accuracy test, performance test and test data in opencv_extra repository, if applicable
Patch to opencv_extra has the same branch name.
- [ ] The feature is well documented and sample code can be built with the project CMake
2023-08-11 13:33:33 +08:00
|
|
|
#if (CV_SIMD || CV_SIMD_SCALABLE)
|
|
|
|
if( len >= VTraits<v_int64>::vlanes() && 2 <= cn && cn <= 4 )
|
2018-07-24 22:27:56 +08:00
|
|
|
vecsplit_<int64, v_int64>(src, dst, len, cn);
|
|
|
|
else
|
|
|
|
#endif
|
|
|
|
split_(src, dst, len, cn);
|
2015-12-03 19:43:37 +08:00
|
|
|
}
|
|
|
|
|
2018-02-06 20:02:51 +08:00
|
|
|
#endif
|
2019-02-22 17:35:32 +08:00
|
|
|
CV_CPU_OPTIMIZATION_NAMESPACE_END
|
|
|
|
}} // namespace
|