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fb8e652c3f
Due to size limit of shared memory, histogram is built on
the global memory for CV_16UC1 case.
The amount of memory needed for building histogram is:
65536 * 4byte = 256KB
and shared memory limit is 48KB typically.
Added test cases for CV_16UC1 and various clip limits.
Added perf tests for CV_16UC1 on both CPU and CUDA code.
There was also a bug in CV_8UC1 case when redistributing
"residual" clipped pixels. Adding the test case where clip
limit is 5.0 exposes this bug.
598 lines
22 KiB
C++
598 lines
22 KiB
C++
/*M///////////////////////////////////////////////////////////////////////////////////////
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//
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// IMPORTANT: READ BEFORE DOWNLOADING, COPYING, INSTALLING OR USING.
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//
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// By downloading, copying, installing or using the software you agree to this license.
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// If you do not agree to this license, do not download, install,
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// copy or use the software.
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//
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//
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// License Agreement
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// For Open Source Computer Vision Library
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//
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// Copyright (C) 2000-2008, Intel Corporation, all rights reserved.
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// Copyright (C) 2009, Willow Garage Inc., all rights reserved.
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// Third party copyrights are property of their respective owners.
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//
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// Redistribution and use in source and binary forms, with or without modification,
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// are permitted provided that the following conditions are met:
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//
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// * Redistribution's of source code must retain the above copyright notice,
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// this list of conditions and the following disclaimer.
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//
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// * Redistribution's in binary form must reproduce the above copyright notice,
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// this list of conditions and the following disclaimer in the documentation
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// and/or other materials provided with the distribution.
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//
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// * The name of the copyright holders may not be used to endorse or promote products
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// derived from this software without specific prior written permission.
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//
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// This software is provided by the copyright holders and contributors "as is" and
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// any express or implied warranties, including, but not limited to, the implied
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// warranties of merchantability and fitness for a particular purpose are disclaimed.
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// In no event shall the Intel Corporation or contributors be liable for any direct,
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// indirect, incidental, special, exemplary, or consequential damages
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// (including, but not limited to, procurement of substitute goods or services;
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// loss of use, data, or profits; or business interruption) however caused
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// and on any theory of liability, whether in contract, strict liability,
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// or tort (including negligence or otherwise) arising in any way out of
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// the use of this software, even if advised of the possibility of such damage.
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//
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//M*/
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#include "precomp.hpp"
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using namespace cv;
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using namespace cv::cuda;
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#if !defined (HAVE_CUDA) || defined (CUDA_DISABLER)
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void cv::cuda::calcHist(InputArray, OutputArray, Stream&) { throw_no_cuda(); }
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void cv::cuda::equalizeHist(InputArray, OutputArray, Stream&) { throw_no_cuda(); }
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cv::Ptr<cv::cuda::CLAHE> cv::cuda::createCLAHE(double, cv::Size) { throw_no_cuda(); return cv::Ptr<cv::cuda::CLAHE>(); }
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void cv::cuda::evenLevels(OutputArray, int, int, int, Stream&) { throw_no_cuda(); }
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void cv::cuda::histEven(InputArray, OutputArray, int, int, int, Stream&) { throw_no_cuda(); }
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void cv::cuda::histEven(InputArray, GpuMat*, int*, int*, int*, Stream&) { throw_no_cuda(); }
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void cv::cuda::histRange(InputArray, OutputArray, InputArray, Stream&) { throw_no_cuda(); }
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void cv::cuda::histRange(InputArray, GpuMat*, const GpuMat*, Stream&) { throw_no_cuda(); }
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#else /* !defined (HAVE_CUDA) */
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////////////////////////////////////////////////////////////////////////
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// calcHist
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namespace hist
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{
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void histogram256(PtrStepSzb src, int* hist, cudaStream_t stream);
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void histogram256(PtrStepSzb src, PtrStepSzb mask, int* hist, cudaStream_t stream);
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}
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void cv::cuda::calcHist(InputArray _src, OutputArray _hist, Stream& stream)
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{
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calcHist(_src, cv::cuda::GpuMat(), _hist, stream);
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}
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void cv::cuda::calcHist(InputArray _src, InputArray _mask, OutputArray _hist, Stream& stream)
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{
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GpuMat src = _src.getGpuMat();
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GpuMat mask = _mask.getGpuMat();
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CV_Assert( src.type() == CV_8UC1 );
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CV_Assert( mask.empty() || mask.type() == CV_8UC1 );
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CV_Assert( mask.empty() || mask.size() == src.size() );
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_hist.create(1, 256, CV_32SC1);
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GpuMat hist = _hist.getGpuMat();
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hist.setTo(Scalar::all(0), stream);
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if (mask.empty())
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hist::histogram256(src, hist.ptr<int>(), StreamAccessor::getStream(stream));
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else
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hist::histogram256(src, mask, hist.ptr<int>(), StreamAccessor::getStream(stream));
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}
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////////////////////////////////////////////////////////////////////////
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// equalizeHist
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namespace hist
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{
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void equalizeHist(PtrStepSzb src, PtrStepSzb dst, const int* lut, cudaStream_t stream);
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}
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void cv::cuda::equalizeHist(InputArray _src, OutputArray _dst, Stream& _stream)
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{
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GpuMat src = getInputMat(_src, _stream);
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CV_Assert( src.type() == CV_8UC1 );
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_dst.create(src.size(), src.type());
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GpuMat dst = _dst.getGpuMat();
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int intBufSize;
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nppSafeCall( nppsIntegralGetBufferSize_32s(256, &intBufSize) );
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size_t bufSize = intBufSize + 2 * 256 * sizeof(int);
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BufferPool pool(_stream);
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GpuMat buf = pool.getBuffer(1, static_cast<int>(bufSize), CV_8UC1);
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GpuMat hist(1, 256, CV_32SC1, buf.data);
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GpuMat lut(1, 256, CV_32SC1, buf.data + 256 * sizeof(int));
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GpuMat intBuf(1, intBufSize, CV_8UC1, buf.data + 2 * 256 * sizeof(int));
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cuda::calcHist(src, hist, _stream);
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cudaStream_t stream = StreamAccessor::getStream(_stream);
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NppStreamHandler h(stream);
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nppSafeCall( nppsIntegral_32s(hist.ptr<Npp32s>(), lut.ptr<Npp32s>(), 256, intBuf.ptr<Npp8u>()) );
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hist::equalizeHist(src, dst, lut.ptr<int>(), stream);
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}
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////////////////////////////////////////////////////////////////////////
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// CLAHE
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namespace clahe
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{
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void calcLut_8U(PtrStepSzb src, PtrStepb lut, int tilesX, int tilesY, int2 tileSize, int clipLimit, float lutScale, cudaStream_t stream);
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void calcLut_16U(PtrStepSzus src, PtrStepus lut, int tilesX, int tilesY, int2 tileSize, int clipLimit, float lutScale, PtrStepSzi hist, cudaStream_t stream);
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template <typename T> void transform(PtrStepSz<T> src, PtrStepSz<T> dst, PtrStep<T> lut, int tilesX, int tilesY, int2 tileSize, cudaStream_t stream);
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}
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namespace
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{
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class CLAHE_Impl : public cv::cuda::CLAHE
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{
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public:
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CLAHE_Impl(double clipLimit = 40.0, int tilesX = 8, int tilesY = 8);
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void apply(cv::InputArray src, cv::OutputArray dst);
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void apply(InputArray src, OutputArray dst, Stream& stream);
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void setClipLimit(double clipLimit);
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double getClipLimit() const;
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void setTilesGridSize(cv::Size tileGridSize);
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cv::Size getTilesGridSize() const;
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void collectGarbage();
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private:
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double clipLimit_;
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int tilesX_;
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int tilesY_;
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GpuMat srcExt_;
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GpuMat lut_;
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GpuMat hist_; // histogram on global memory for CV_16UC1 case
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};
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CLAHE_Impl::CLAHE_Impl(double clipLimit, int tilesX, int tilesY) :
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clipLimit_(clipLimit), tilesX_(tilesX), tilesY_(tilesY)
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{
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}
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void CLAHE_Impl::apply(cv::InputArray _src, cv::OutputArray _dst)
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{
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apply(_src, _dst, Stream::Null());
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}
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void CLAHE_Impl::apply(InputArray _src, OutputArray _dst, Stream& s)
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{
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GpuMat src = _src.getGpuMat();
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const int type = src.type();
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CV_Assert( type == CV_8UC1 || type == CV_16UC1 );
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_dst.create( src.size(), type );
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GpuMat dst = _dst.getGpuMat();
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const int histSize = type == CV_8UC1 ? 256 : 65536;
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ensureSizeIsEnough(tilesX_ * tilesY_, histSize, type, lut_);
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cudaStream_t stream = StreamAccessor::getStream(s);
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cv::Size tileSize;
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GpuMat srcForLut;
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if (src.cols % tilesX_ == 0 && src.rows % tilesY_ == 0)
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{
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tileSize = cv::Size(src.cols / tilesX_, src.rows / tilesY_);
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srcForLut = src;
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}
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else
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{
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#ifndef HAVE_OPENCV_CUDAARITHM
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throw_no_cuda();
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#else
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cv::cuda::copyMakeBorder(src, srcExt_, 0, tilesY_ - (src.rows % tilesY_), 0, tilesX_ - (src.cols % tilesX_), cv::BORDER_REFLECT_101, cv::Scalar(), s);
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#endif
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tileSize = cv::Size(srcExt_.cols / tilesX_, srcExt_.rows / tilesY_);
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srcForLut = srcExt_;
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}
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const int tileSizeTotal = tileSize.area();
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const float lutScale = static_cast<float>(histSize - 1) / tileSizeTotal;
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int clipLimit = 0;
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if (clipLimit_ > 0.0)
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{
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clipLimit = static_cast<int>(clipLimit_ * tileSizeTotal / histSize);
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clipLimit = std::max(clipLimit, 1);
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}
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if (type == CV_8UC1)
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clahe::calcLut_8U(srcForLut, lut_, tilesX_, tilesY_, make_int2(tileSize.width, tileSize.height), clipLimit, lutScale, stream);
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else // type == CV_16UC1
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{
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ensureSizeIsEnough(tilesX_ * tilesY_, histSize, CV_32SC1, hist_);
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clahe::calcLut_16U(srcForLut, lut_, tilesX_, tilesY_, make_int2(tileSize.width, tileSize.height), clipLimit, lutScale, hist_, stream);
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}
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if (type == CV_8UC1)
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clahe::transform<uchar>(src, dst, lut_, tilesX_, tilesY_, make_int2(tileSize.width, tileSize.height), stream);
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else // type == CV_16UC1
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clahe::transform<ushort>(src, dst, lut_, tilesX_, tilesY_, make_int2(tileSize.width, tileSize.height), stream);
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}
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void CLAHE_Impl::setClipLimit(double clipLimit)
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{
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clipLimit_ = clipLimit;
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}
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double CLAHE_Impl::getClipLimit() const
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{
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return clipLimit_;
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}
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void CLAHE_Impl::setTilesGridSize(cv::Size tileGridSize)
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{
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tilesX_ = tileGridSize.width;
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tilesY_ = tileGridSize.height;
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}
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cv::Size CLAHE_Impl::getTilesGridSize() const
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{
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return cv::Size(tilesX_, tilesY_);
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}
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void CLAHE_Impl::collectGarbage()
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{
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srcExt_.release();
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lut_.release();
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}
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}
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cv::Ptr<cv::cuda::CLAHE> cv::cuda::createCLAHE(double clipLimit, cv::Size tileGridSize)
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{
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return makePtr<CLAHE_Impl>(clipLimit, tileGridSize.width, tileGridSize.height);
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}
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////////////////////////////////////////////////////////////////////////
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// NPP Histogram
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namespace
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{
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typedef NppStatus (*get_buf_size_c1_t)(NppiSize oSizeROI, int nLevels, int* hpBufferSize);
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typedef NppStatus (*get_buf_size_c4_t)(NppiSize oSizeROI, int nLevels[], int* hpBufferSize);
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template<int SDEPTH> struct NppHistogramEvenFuncC1
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{
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typedef typename NPPTypeTraits<SDEPTH>::npp_type src_t;
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typedef NppStatus (*func_ptr)(const src_t* pSrc, int nSrcStep, NppiSize oSizeROI, Npp32s * pHist,
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int nLevels, Npp32s nLowerLevel, Npp32s nUpperLevel, Npp8u * pBuffer);
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};
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template<int SDEPTH> struct NppHistogramEvenFuncC4
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{
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typedef typename NPPTypeTraits<SDEPTH>::npp_type src_t;
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typedef NppStatus (*func_ptr)(const src_t* pSrc, int nSrcStep, NppiSize oSizeROI,
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Npp32s * pHist[4], int nLevels[4], Npp32s nLowerLevel[4], Npp32s nUpperLevel[4], Npp8u * pBuffer);
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};
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template<int SDEPTH, typename NppHistogramEvenFuncC1<SDEPTH>::func_ptr func, get_buf_size_c1_t get_buf_size>
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struct NppHistogramEvenC1
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{
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typedef typename NppHistogramEvenFuncC1<SDEPTH>::src_t src_t;
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static void hist(const GpuMat& src, OutputArray _hist, int histSize, int lowerLevel, int upperLevel, Stream& stream)
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{
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const int levels = histSize + 1;
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_hist.create(1, histSize, CV_32S);
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GpuMat hist = _hist.getGpuMat();
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NppiSize sz;
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sz.width = src.cols;
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sz.height = src.rows;
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int buf_size;
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get_buf_size(sz, levels, &buf_size);
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BufferPool pool(stream);
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GpuMat buf = pool.getBuffer(1, buf_size, CV_8UC1);
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NppStreamHandler h(stream);
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nppSafeCall( func(src.ptr<src_t>(), static_cast<int>(src.step), sz, hist.ptr<Npp32s>(), levels,
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lowerLevel, upperLevel, buf.ptr<Npp8u>()) );
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if (!stream)
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cudaSafeCall( cudaDeviceSynchronize() );
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}
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};
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template<int SDEPTH, typename NppHistogramEvenFuncC4<SDEPTH>::func_ptr func, get_buf_size_c4_t get_buf_size>
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struct NppHistogramEvenC4
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{
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typedef typename NppHistogramEvenFuncC4<SDEPTH>::src_t src_t;
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static void hist(const GpuMat& src, GpuMat hist[4], int histSize[4], int lowerLevel[4], int upperLevel[4], Stream& stream)
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{
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int levels[] = {histSize[0] + 1, histSize[1] + 1, histSize[2] + 1, histSize[3] + 1};
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hist[0].create(1, histSize[0], CV_32S);
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hist[1].create(1, histSize[1], CV_32S);
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hist[2].create(1, histSize[2], CV_32S);
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hist[3].create(1, histSize[3], CV_32S);
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NppiSize sz;
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sz.width = src.cols;
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sz.height = src.rows;
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Npp32s* pHist[] = {hist[0].ptr<Npp32s>(), hist[1].ptr<Npp32s>(), hist[2].ptr<Npp32s>(), hist[3].ptr<Npp32s>()};
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int buf_size;
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get_buf_size(sz, levels, &buf_size);
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BufferPool pool(stream);
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GpuMat buf = pool.getBuffer(1, buf_size, CV_8UC1);
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NppStreamHandler h(stream);
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nppSafeCall( func(src.ptr<src_t>(), static_cast<int>(src.step), sz, pHist, levels, lowerLevel, upperLevel, buf.ptr<Npp8u>()) );
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if (!stream)
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cudaSafeCall( cudaDeviceSynchronize() );
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}
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};
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template<int SDEPTH> struct NppHistogramRangeFuncC1
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{
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typedef typename NPPTypeTraits<SDEPTH>::npp_type src_t;
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typedef Npp32s level_t;
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enum {LEVEL_TYPE_CODE=CV_32SC1};
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typedef NppStatus (*func_ptr)(const src_t* pSrc, int nSrcStep, NppiSize oSizeROI, Npp32s* pHist,
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const Npp32s* pLevels, int nLevels, Npp8u* pBuffer);
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};
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template<> struct NppHistogramRangeFuncC1<CV_32F>
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{
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typedef Npp32f src_t;
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typedef Npp32f level_t;
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enum {LEVEL_TYPE_CODE=CV_32FC1};
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typedef NppStatus (*func_ptr)(const Npp32f* pSrc, int nSrcStep, NppiSize oSizeROI, Npp32s* pHist,
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const Npp32f* pLevels, int nLevels, Npp8u* pBuffer);
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};
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template<int SDEPTH> struct NppHistogramRangeFuncC4
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{
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typedef typename NPPTypeTraits<SDEPTH>::npp_type src_t;
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typedef Npp32s level_t;
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enum {LEVEL_TYPE_CODE=CV_32SC1};
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typedef NppStatus (*func_ptr)(const src_t* pSrc, int nSrcStep, NppiSize oSizeROI, Npp32s* pHist[4],
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const Npp32s* pLevels[4], int nLevels[4], Npp8u* pBuffer);
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};
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template<> struct NppHistogramRangeFuncC4<CV_32F>
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{
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typedef Npp32f src_t;
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typedef Npp32f level_t;
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enum {LEVEL_TYPE_CODE=CV_32FC1};
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typedef NppStatus (*func_ptr)(const Npp32f* pSrc, int nSrcStep, NppiSize oSizeROI, Npp32s* pHist[4],
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const Npp32f* pLevels[4], int nLevels[4], Npp8u* pBuffer);
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};
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template<int SDEPTH, typename NppHistogramRangeFuncC1<SDEPTH>::func_ptr func, get_buf_size_c1_t get_buf_size>
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struct NppHistogramRangeC1
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{
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typedef typename NppHistogramRangeFuncC1<SDEPTH>::src_t src_t;
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typedef typename NppHistogramRangeFuncC1<SDEPTH>::level_t level_t;
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enum {LEVEL_TYPE_CODE=NppHistogramRangeFuncC1<SDEPTH>::LEVEL_TYPE_CODE};
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static void hist(const GpuMat& src, OutputArray _hist, const GpuMat& levels, Stream& stream)
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{
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CV_Assert( levels.type() == LEVEL_TYPE_CODE && levels.rows == 1 );
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_hist.create(1, levels.cols - 1, CV_32S);
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GpuMat hist = _hist.getGpuMat();
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NppiSize sz;
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sz.width = src.cols;
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sz.height = src.rows;
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int buf_size;
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get_buf_size(sz, levels.cols, &buf_size);
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BufferPool pool(stream);
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GpuMat buf = pool.getBuffer(1, buf_size, CV_8UC1);
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NppStreamHandler h(stream);
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nppSafeCall( func(src.ptr<src_t>(), static_cast<int>(src.step), sz, hist.ptr<Npp32s>(), levels.ptr<level_t>(), levels.cols, buf.ptr<Npp8u>()) );
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if (stream == 0)
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cudaSafeCall( cudaDeviceSynchronize() );
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}
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};
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template<int SDEPTH, typename NppHistogramRangeFuncC4<SDEPTH>::func_ptr func, get_buf_size_c4_t get_buf_size>
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struct NppHistogramRangeC4
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{
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typedef typename NppHistogramRangeFuncC4<SDEPTH>::src_t src_t;
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typedef typename NppHistogramRangeFuncC1<SDEPTH>::level_t level_t;
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enum {LEVEL_TYPE_CODE=NppHistogramRangeFuncC1<SDEPTH>::LEVEL_TYPE_CODE};
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static void hist(const GpuMat& src, GpuMat hist[4], const GpuMat levels[4], Stream& stream)
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{
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CV_Assert( levels[0].type() == LEVEL_TYPE_CODE && levels[0].rows == 1 );
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CV_Assert( levels[1].type() == LEVEL_TYPE_CODE && levels[1].rows == 1 );
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CV_Assert( levels[2].type() == LEVEL_TYPE_CODE && levels[2].rows == 1 );
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CV_Assert( levels[3].type() == LEVEL_TYPE_CODE && levels[3].rows == 1 );
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hist[0].create(1, levels[0].cols - 1, CV_32S);
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hist[1].create(1, levels[1].cols - 1, CV_32S);
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hist[2].create(1, levels[2].cols - 1, CV_32S);
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hist[3].create(1, levels[3].cols - 1, CV_32S);
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Npp32s* pHist[] = {hist[0].ptr<Npp32s>(), hist[1].ptr<Npp32s>(), hist[2].ptr<Npp32s>(), hist[3].ptr<Npp32s>()};
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int nLevels[] = {levels[0].cols, levels[1].cols, levels[2].cols, levels[3].cols};
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const level_t* pLevels[] = {levels[0].ptr<level_t>(), levels[1].ptr<level_t>(), levels[2].ptr<level_t>(), levels[3].ptr<level_t>()};
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NppiSize sz;
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sz.width = src.cols;
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sz.height = src.rows;
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int buf_size;
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get_buf_size(sz, nLevels, &buf_size);
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BufferPool pool(stream);
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GpuMat buf = pool.getBuffer(1, buf_size, CV_8UC1);
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NppStreamHandler h(stream);
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nppSafeCall( func(src.ptr<src_t>(), static_cast<int>(src.step), sz, pHist, pLevels, nLevels, buf.ptr<Npp8u>()) );
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if (stream == 0)
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cudaSafeCall( cudaDeviceSynchronize() );
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}
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};
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}
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void cv::cuda::evenLevels(OutputArray _levels, int nLevels, int lowerLevel, int upperLevel, Stream& stream)
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{
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const int kind = _levels.kind();
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_levels.create(1, nLevels, CV_32SC1);
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Mat host_levels;
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if (kind == _InputArray::CUDA_GPU_MAT)
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host_levels.create(1, nLevels, CV_32SC1);
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else
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host_levels = _levels.getMat();
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nppSafeCall( nppiEvenLevelsHost_32s(host_levels.ptr<Npp32s>(), nLevels, lowerLevel, upperLevel) );
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if (kind == _InputArray::CUDA_GPU_MAT)
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_levels.getGpuMatRef().upload(host_levels, stream);
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}
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namespace hist
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{
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void histEven8u(PtrStepSzb src, int* hist, int binCount, int lowerLevel, int upperLevel, cudaStream_t stream);
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}
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namespace
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{
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void histEven8u(const GpuMat& src, GpuMat& hist, int histSize, int lowerLevel, int upperLevel, cudaStream_t stream)
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{
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hist.create(1, histSize, CV_32S);
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cudaSafeCall( cudaMemsetAsync(hist.data, 0, histSize * sizeof(int), stream) );
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hist::histEven8u(src, hist.ptr<int>(), histSize, lowerLevel, upperLevel, stream);
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}
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}
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void cv::cuda::histEven(InputArray _src, OutputArray hist, int histSize, int lowerLevel, int upperLevel, Stream& stream)
|
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{
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typedef void (*hist_t)(const GpuMat& src, OutputArray hist, int levels, int lowerLevel, int upperLevel, Stream& stream);
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static const hist_t hist_callers[] =
|
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{
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NppHistogramEvenC1<CV_8U , nppiHistogramEven_8u_C1R , nppiHistogramEvenGetBufferSize_8u_C1R >::hist,
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0,
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NppHistogramEvenC1<CV_16U, nppiHistogramEven_16u_C1R, nppiHistogramEvenGetBufferSize_16u_C1R>::hist,
|
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NppHistogramEvenC1<CV_16S, nppiHistogramEven_16s_C1R, nppiHistogramEvenGetBufferSize_16s_C1R>::hist
|
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};
|
|
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GpuMat src = _src.getGpuMat();
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|
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if (src.depth() == CV_8U && deviceSupports(FEATURE_SET_COMPUTE_30))
|
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{
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histEven8u(src, hist.getGpuMatRef(), histSize, lowerLevel, upperLevel, StreamAccessor::getStream(stream));
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return;
|
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}
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CV_Assert( src.type() == CV_8UC1 || src.type() == CV_16UC1 || src.type() == CV_16SC1 );
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hist_callers[src.depth()](src, hist, histSize, lowerLevel, upperLevel, stream);
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}
|
|
|
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void cv::cuda::histEven(InputArray _src, GpuMat hist[4], int histSize[4], int lowerLevel[4], int upperLevel[4], Stream& stream)
|
|
{
|
|
typedef void (*hist_t)(const GpuMat& src, GpuMat hist[4], int levels[4], int lowerLevel[4], int upperLevel[4], Stream& stream);
|
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static const hist_t hist_callers[] =
|
|
{
|
|
NppHistogramEvenC4<CV_8U , nppiHistogramEven_8u_C4R , nppiHistogramEvenGetBufferSize_8u_C4R >::hist,
|
|
0,
|
|
NppHistogramEvenC4<CV_16U, nppiHistogramEven_16u_C4R, nppiHistogramEvenGetBufferSize_16u_C4R>::hist,
|
|
NppHistogramEvenC4<CV_16S, nppiHistogramEven_16s_C4R, nppiHistogramEvenGetBufferSize_16s_C4R>::hist
|
|
};
|
|
|
|
GpuMat src = _src.getGpuMat();
|
|
|
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CV_Assert( src.type() == CV_8UC4 || src.type() == CV_16UC4 || src.type() == CV_16SC4 );
|
|
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hist_callers[src.depth()](src, hist, histSize, lowerLevel, upperLevel, stream);
|
|
}
|
|
|
|
void cv::cuda::histRange(InputArray _src, OutputArray hist, InputArray _levels, Stream& stream)
|
|
{
|
|
typedef void (*hist_t)(const GpuMat& src, OutputArray hist, const GpuMat& levels, Stream& stream);
|
|
static const hist_t hist_callers[] =
|
|
{
|
|
NppHistogramRangeC1<CV_8U , nppiHistogramRange_8u_C1R , nppiHistogramRangeGetBufferSize_8u_C1R >::hist,
|
|
0,
|
|
NppHistogramRangeC1<CV_16U, nppiHistogramRange_16u_C1R, nppiHistogramRangeGetBufferSize_16u_C1R>::hist,
|
|
NppHistogramRangeC1<CV_16S, nppiHistogramRange_16s_C1R, nppiHistogramRangeGetBufferSize_16s_C1R>::hist,
|
|
0,
|
|
NppHistogramRangeC1<CV_32F, nppiHistogramRange_32f_C1R, nppiHistogramRangeGetBufferSize_32f_C1R>::hist
|
|
};
|
|
|
|
GpuMat src = _src.getGpuMat();
|
|
GpuMat levels = _levels.getGpuMat();
|
|
|
|
CV_Assert( src.type() == CV_8UC1 || src.type() == CV_16UC1 || src.type() == CV_16SC1 || src.type() == CV_32FC1 );
|
|
|
|
hist_callers[src.depth()](src, hist, levels, stream);
|
|
}
|
|
|
|
void cv::cuda::histRange(InputArray _src, GpuMat hist[4], const GpuMat levels[4], Stream& stream)
|
|
{
|
|
typedef void (*hist_t)(const GpuMat& src, GpuMat hist[4], const GpuMat levels[4], Stream& stream);
|
|
static const hist_t hist_callers[] =
|
|
{
|
|
NppHistogramRangeC4<CV_8U , nppiHistogramRange_8u_C4R , nppiHistogramRangeGetBufferSize_8u_C4R >::hist,
|
|
0,
|
|
NppHistogramRangeC4<CV_16U, nppiHistogramRange_16u_C4R, nppiHistogramRangeGetBufferSize_16u_C4R>::hist,
|
|
NppHistogramRangeC4<CV_16S, nppiHistogramRange_16s_C4R, nppiHistogramRangeGetBufferSize_16s_C4R>::hist,
|
|
0,
|
|
NppHistogramRangeC4<CV_32F, nppiHistogramRange_32f_C4R, nppiHistogramRangeGetBufferSize_32f_C4R>::hist
|
|
};
|
|
|
|
GpuMat src = _src.getGpuMat();
|
|
|
|
CV_Assert( src.type() == CV_8UC4 || src.type() == CV_16UC4 || src.type() == CV_16SC4 || src.type() == CV_32FC4 );
|
|
|
|
hist_callers[src.depth()](src, hist, levels, stream);
|
|
}
|
|
|
|
#endif /* !defined (HAVE_CUDA) */
|