mirror of
https://github.com/cesanta/mongoose.git
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403 lines
16 KiB
C
403 lines
16 KiB
C
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/*
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* Copyright 2021 NXP
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* All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include "fsl_common.h"
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#include "fsl_debug_console.h"
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#include "board.h"
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#if defined(SDK_I2C_BASED_COMPONENT_USED) && SDK_I2C_BASED_COMPONENT_USED
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#include "fsl_lpi2c.h"
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#endif /* SDK_I2C_BASED_COMPONENT_USED */
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#include "fsl_iomuxc.h"
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/*******************************************************************************
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* Variables
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******************************************************************************/
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/*******************************************************************************
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* Code
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******************************************************************************/
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/* Get debug console frequency. */
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uint32_t BOARD_DebugConsoleSrcFreq(void)
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{
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uint32_t freq;
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/* To make it simple, we assume default PLL and divider settings, and the only variable
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from application is use PLL3 source or OSC source */
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if (CLOCK_GetMux(kCLOCK_UartMux) == 0) /* PLL3 div6 80M */
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{
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freq = (CLOCK_GetPllFreq(kCLOCK_PllUsb1) / 6U) / (CLOCK_GetDiv(kCLOCK_UartDiv) + 1U);
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}
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else
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{
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freq = CLOCK_GetOscFreq() / (CLOCK_GetDiv(kCLOCK_UartDiv) + 1U);
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}
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return freq;
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}
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/* Initialize debug console. */
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void BOARD_InitDebugConsole(void)
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{
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uint32_t uartClkSrcFreq = BOARD_DebugConsoleSrcFreq();
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DbgConsole_Init(BOARD_DEBUG_UART_INSTANCE, BOARD_DEBUG_UART_BAUDRATE, BOARD_DEBUG_UART_TYPE, uartClkSrcFreq);
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}
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#if defined(SDK_I2C_BASED_COMPONENT_USED) && SDK_I2C_BASED_COMPONENT_USED
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void BOARD_LPI2C_Init(LPI2C_Type *base, uint32_t clkSrc_Hz)
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{
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lpi2c_master_config_t lpi2cConfig = {0};
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/*
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* lpi2cConfig.debugEnable = false;
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* lpi2cConfig.ignoreAck = false;
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* lpi2cConfig.pinConfig = kLPI2C_2PinOpenDrain;
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* lpi2cConfig.baudRate_Hz = 100000U;
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* lpi2cConfig.busIdleTimeout_ns = 0;
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* lpi2cConfig.pinLowTimeout_ns = 0;
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* lpi2cConfig.sdaGlitchFilterWidth_ns = 0;
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* lpi2cConfig.sclGlitchFilterWidth_ns = 0;
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*/
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LPI2C_MasterGetDefaultConfig(&lpi2cConfig);
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LPI2C_MasterInit(base, &lpi2cConfig, clkSrc_Hz);
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}
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status_t BOARD_LPI2C_Send(LPI2C_Type *base,
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uint8_t deviceAddress,
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uint32_t subAddress,
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uint8_t subAddressSize,
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uint8_t *txBuff,
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uint8_t txBuffSize)
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{
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lpi2c_master_transfer_t xfer;
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xfer.flags = kLPI2C_TransferDefaultFlag;
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xfer.slaveAddress = deviceAddress;
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xfer.direction = kLPI2C_Write;
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xfer.subaddress = subAddress;
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xfer.subaddressSize = subAddressSize;
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xfer.data = txBuff;
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xfer.dataSize = txBuffSize;
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return LPI2C_MasterTransferBlocking(base, &xfer);
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}
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status_t BOARD_LPI2C_Receive(LPI2C_Type *base,
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uint8_t deviceAddress,
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uint32_t subAddress,
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uint8_t subAddressSize,
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uint8_t *rxBuff,
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uint8_t rxBuffSize)
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{
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lpi2c_master_transfer_t xfer;
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xfer.flags = kLPI2C_TransferDefaultFlag;
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xfer.slaveAddress = deviceAddress;
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xfer.direction = kLPI2C_Read;
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xfer.subaddress = subAddress;
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xfer.subaddressSize = subAddressSize;
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xfer.data = rxBuff;
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xfer.dataSize = rxBuffSize;
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return LPI2C_MasterTransferBlocking(base, &xfer);
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}
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status_t BOARD_LPI2C_SendSCCB(LPI2C_Type *base,
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uint8_t deviceAddress,
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uint32_t subAddress,
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uint8_t subAddressSize,
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uint8_t *txBuff,
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uint8_t txBuffSize)
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{
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lpi2c_master_transfer_t xfer;
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xfer.flags = kLPI2C_TransferDefaultFlag;
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xfer.slaveAddress = deviceAddress;
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xfer.direction = kLPI2C_Write;
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xfer.subaddress = subAddress;
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xfer.subaddressSize = subAddressSize;
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xfer.data = txBuff;
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xfer.dataSize = txBuffSize;
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return LPI2C_MasterTransferBlocking(base, &xfer);
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}
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status_t BOARD_LPI2C_ReceiveSCCB(LPI2C_Type *base,
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uint8_t deviceAddress,
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uint32_t subAddress,
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uint8_t subAddressSize,
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uint8_t *rxBuff,
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uint8_t rxBuffSize)
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{
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status_t status;
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lpi2c_master_transfer_t xfer;
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xfer.flags = kLPI2C_TransferDefaultFlag;
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xfer.slaveAddress = deviceAddress;
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xfer.direction = kLPI2C_Write;
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xfer.subaddress = subAddress;
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xfer.subaddressSize = subAddressSize;
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xfer.data = NULL;
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xfer.dataSize = 0;
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status = LPI2C_MasterTransferBlocking(base, &xfer);
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if (kStatus_Success == status)
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{
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xfer.subaddressSize = 0;
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xfer.direction = kLPI2C_Read;
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xfer.data = rxBuff;
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xfer.dataSize = rxBuffSize;
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status = LPI2C_MasterTransferBlocking(base, &xfer);
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}
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return status;
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}
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void BOARD_Accel_I2C_Init(void)
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{
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BOARD_LPI2C_Init(BOARD_ACCEL_I2C_BASEADDR, BOARD_ACCEL_I2C_CLOCK_FREQ);
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}
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status_t BOARD_Accel_I2C_Send(uint8_t deviceAddress, uint32_t subAddress, uint8_t subaddressSize, uint32_t txBuff)
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{
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uint8_t data = (uint8_t)txBuff;
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return BOARD_LPI2C_Send(BOARD_ACCEL_I2C_BASEADDR, deviceAddress, subAddress, subaddressSize, &data, 1);
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}
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status_t BOARD_Accel_I2C_Receive(
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uint8_t deviceAddress, uint32_t subAddress, uint8_t subaddressSize, uint8_t *rxBuff, uint8_t rxBuffSize)
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{
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return BOARD_LPI2C_Receive(BOARD_ACCEL_I2C_BASEADDR, deviceAddress, subAddress, subaddressSize, rxBuff, rxBuffSize);
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}
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void BOARD_Codec_I2C_Init(void)
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{
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BOARD_LPI2C_Init(BOARD_CODEC_I2C_BASEADDR, BOARD_CODEC_I2C_CLOCK_FREQ);
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}
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status_t BOARD_Codec_I2C_Send(
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uint8_t deviceAddress, uint32_t subAddress, uint8_t subAddressSize, const uint8_t *txBuff, uint8_t txBuffSize)
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{
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return BOARD_LPI2C_Send(BOARD_CODEC_I2C_BASEADDR, deviceAddress, subAddress, subAddressSize, (uint8_t *)txBuff,
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txBuffSize);
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}
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status_t BOARD_Codec_I2C_Receive(
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uint8_t deviceAddress, uint32_t subAddress, uint8_t subAddressSize, uint8_t *rxBuff, uint8_t rxBuffSize)
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{
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return BOARD_LPI2C_Receive(BOARD_CODEC_I2C_BASEADDR, deviceAddress, subAddress, subAddressSize, rxBuff, rxBuffSize);
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}
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void BOARD_Camera_I2C_Init(void)
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{
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CLOCK_SetMux(kCLOCK_Lpi2cMux, BOARD_CAMERA_I2C_CLOCK_SOURCE_SELECT);
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CLOCK_SetDiv(kCLOCK_Lpi2cDiv, BOARD_CAMERA_I2C_CLOCK_SOURCE_DIVIDER);
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BOARD_LPI2C_Init(BOARD_CAMERA_I2C_BASEADDR, BOARD_CAMERA_I2C_CLOCK_FREQ);
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}
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status_t BOARD_Camera_I2C_Send(
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uint8_t deviceAddress, uint32_t subAddress, uint8_t subAddressSize, const uint8_t *txBuff, uint8_t txBuffSize)
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{
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return BOARD_LPI2C_Send(BOARD_CAMERA_I2C_BASEADDR, deviceAddress, subAddress, subAddressSize, (uint8_t *)txBuff,
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txBuffSize);
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}
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status_t BOARD_Camera_I2C_Receive(
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uint8_t deviceAddress, uint32_t subAddress, uint8_t subAddressSize, uint8_t *rxBuff, uint8_t rxBuffSize)
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{
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return BOARD_LPI2C_Receive(BOARD_CAMERA_I2C_BASEADDR, deviceAddress, subAddress, subAddressSize, rxBuff,
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rxBuffSize);
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}
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status_t BOARD_Camera_I2C_SendSCCB(
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uint8_t deviceAddress, uint32_t subAddress, uint8_t subAddressSize, const uint8_t *txBuff, uint8_t txBuffSize)
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{
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return BOARD_LPI2C_SendSCCB(BOARD_CAMERA_I2C_BASEADDR, deviceAddress, subAddress, subAddressSize, (uint8_t *)txBuff,
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txBuffSize);
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}
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status_t BOARD_Camera_I2C_ReceiveSCCB(
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uint8_t deviceAddress, uint32_t subAddress, uint8_t subAddressSize, uint8_t *rxBuff, uint8_t rxBuffSize)
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{
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return BOARD_LPI2C_ReceiveSCCB(BOARD_CAMERA_I2C_BASEADDR, deviceAddress, subAddress, subAddressSize, rxBuff,
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rxBuffSize);
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}
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status_t BOARD_Touch_I2C_Send(
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uint8_t deviceAddress, uint32_t subAddress, uint8_t subAddressSize, const uint8_t *txBuff, uint8_t txBuffSize)
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{
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return BOARD_LPI2C_Send(BOARD_TOUCH_I2C_BASEADDR, deviceAddress, subAddress, subAddressSize, (uint8_t *)txBuff,
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txBuffSize);
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}
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status_t BOARD_Touch_I2C_Receive(
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uint8_t deviceAddress, uint32_t subAddress, uint8_t subAddressSize, uint8_t *rxBuff, uint8_t rxBuffSize)
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{
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return BOARD_LPI2C_Receive(BOARD_TOUCH_I2C_BASEADDR, deviceAddress, subAddress, subAddressSize, rxBuff, rxBuffSize);
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}
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#endif /* SDK_I2C_BASED_COMPONENT_USED */
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/* MPU configuration. */
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void BOARD_ConfigMPU(void)
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{
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#if defined(__CC_ARM) || defined(__ARMCC_VERSION)
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extern uint32_t Image$$RW_m_ncache$$Base[];
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/* RW_m_ncache_unused is a auxiliary region which is used to get the whole size of noncache section */
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extern uint32_t Image$$RW_m_ncache_unused$$Base[];
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extern uint32_t Image$$RW_m_ncache_unused$$ZI$$Limit[];
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uint32_t nonCacheStart = (uint32_t)Image$$RW_m_ncache$$Base;
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uint32_t size = ((uint32_t)Image$$RW_m_ncache_unused$$Base == nonCacheStart) ?
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0 :
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((uint32_t)Image$$RW_m_ncache_unused$$ZI$$Limit - nonCacheStart);
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#elif defined(__MCUXPRESSO)
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extern uint32_t __base_NCACHE_REGION;
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extern uint32_t __top_NCACHE_REGION;
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uint32_t nonCacheStart = (uint32_t)(&__base_NCACHE_REGION);
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uint32_t size = (uint32_t)(&__top_NCACHE_REGION) - nonCacheStart;
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#elif defined(__ICCARM__) || defined(__GNUC__)
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extern uint32_t __NCACHE_REGION_START[];
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extern uint32_t __NCACHE_REGION_SIZE[];
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uint32_t nonCacheStart = (uint32_t)__NCACHE_REGION_START;
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uint32_t size = (uint32_t)__NCACHE_REGION_SIZE;
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#endif
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volatile uint32_t i = 0;
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/* Disable I cache and D cache */
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if (SCB_CCR_IC_Msk == (SCB_CCR_IC_Msk & SCB->CCR))
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{
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SCB_DisableICache();
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}
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if (SCB_CCR_DC_Msk == (SCB_CCR_DC_Msk & SCB->CCR))
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{
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SCB_DisableDCache();
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}
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/* Disable MPU */
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ARM_MPU_Disable();
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/* MPU configure:
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* Use ARM_MPU_RASR(DisableExec, AccessPermission, TypeExtField, IsShareable, IsCacheable, IsBufferable,
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* SubRegionDisable, Size)
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* API in mpu_armv7.h.
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* param DisableExec Instruction access (XN) disable bit,0=instruction fetches enabled, 1=instruction fetches
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* disabled.
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* param AccessPermission Data access permissions, allows you to configure read/write access for User and
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* Privileged mode.
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* Use MACROS defined in mpu_armv7.h:
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* ARM_MPU_AP_NONE/ARM_MPU_AP_PRIV/ARM_MPU_AP_URO/ARM_MPU_AP_FULL/ARM_MPU_AP_PRO/ARM_MPU_AP_RO
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* Combine TypeExtField/IsShareable/IsCacheable/IsBufferable to configure MPU memory access attributes.
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* TypeExtField IsShareable IsCacheable IsBufferable Memory Attribute Shareability Cache
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* 0 x 0 0 Strongly Ordered shareable
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* 0 x 0 1 Device shareable
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* 0 0 1 0 Normal not shareable Outer and inner write
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* through no write allocate
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* 0 0 1 1 Normal not shareable Outer and inner write
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* back no write allocate
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* 0 1 1 0 Normal shareable Outer and inner write
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* through no write allocate
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* 0 1 1 1 Normal shareable Outer and inner write
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* back no write allocate
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* 1 0 0 0 Normal not shareable outer and inner
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* noncache
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* 1 1 0 0 Normal shareable outer and inner
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* noncache
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* 1 0 1 1 Normal not shareable outer and inner write
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* back write/read acllocate
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* 1 1 1 1 Normal shareable outer and inner write
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* back write/read acllocate
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* 2 x 0 0 Device not shareable
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* Above are normal use settings, if your want to see more details or want to config different inner/outter cache
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* policy.
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* please refer to Table 4-55 /4-56 in arm cortex-M7 generic user guide <dui0646b_cortex_m7_dgug.pdf>
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* param SubRegionDisable Sub-region disable field. 0=sub-region is enabled, 1=sub-region is disabled.
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* param Size Region size of the region to be configured. use ARM_MPU_REGION_SIZE_xxx MACRO in
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* mpu_armv7.h.
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*/
|
||
|
|
|
||
|
|
/*
|
||
|
|
* Add default region to deny access to whole address space to workaround speculative prefetch.
|
||
|
|
* Refer to Arm errata 1013783-B for more details.
|
||
|
|
*
|
||
|
|
*/
|
||
|
|
/* Region 0 setting: Instruction access disabled, No data access permission. */
|
||
|
|
MPU->RBAR = ARM_MPU_RBAR(0, 0x00000000U);
|
||
|
|
MPU->RASR = ARM_MPU_RASR(1, ARM_MPU_AP_NONE, 0, 0, 0, 0, 0, ARM_MPU_REGION_SIZE_4GB);
|
||
|
|
|
||
|
|
/* Region 1 setting: Memory with Device type, not shareable, non-cacheable. */
|
||
|
|
MPU->RBAR = ARM_MPU_RBAR(1, 0x80000000U);
|
||
|
|
MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 2, 0, 0, 0, 0, ARM_MPU_REGION_SIZE_512MB);
|
||
|
|
|
||
|
|
/* Region 2 setting: Memory with Device type, not shareable, non-cacheable. */
|
||
|
|
MPU->RBAR = ARM_MPU_RBAR(2, 0x60000000U);
|
||
|
|
MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 2, 0, 0, 0, 0, ARM_MPU_REGION_SIZE_512MB);
|
||
|
|
|
||
|
|
#if defined(XIP_EXTERNAL_FLASH) && (XIP_EXTERNAL_FLASH == 1)
|
||
|
|
/* Region 3 setting: Memory with Normal type, not shareable, outer/inner write back. */
|
||
|
|
MPU->RBAR = ARM_MPU_RBAR(3, 0x60000000U);
|
||
|
|
MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_RO, 0, 0, 1, 1, 0, ARM_MPU_REGION_SIZE_8MB);
|
||
|
|
#endif
|
||
|
|
|
||
|
|
/* Region 4 setting: Memory with Device type, not shareable, non-cacheable. */
|
||
|
|
MPU->RBAR = ARM_MPU_RBAR(4, 0x00000000U);
|
||
|
|
MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 2, 0, 0, 0, 0, ARM_MPU_REGION_SIZE_1GB);
|
||
|
|
|
||
|
|
/* Region 5 setting: Memory with Normal type, not shareable, outer/inner write back */
|
||
|
|
MPU->RBAR = ARM_MPU_RBAR(5, 0x00000000U);
|
||
|
|
MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 0, 0, 1, 1, 0, ARM_MPU_REGION_SIZE_128KB);
|
||
|
|
|
||
|
|
/* Region 6 setting: Memory with Normal type, not shareable, outer/inner write back */
|
||
|
|
MPU->RBAR = ARM_MPU_RBAR(6, 0x20000000U);
|
||
|
|
MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 0, 0, 1, 1, 0, ARM_MPU_REGION_SIZE_128KB);
|
||
|
|
|
||
|
|
/* Region 7 setting: Memory with Normal type, not shareable, outer/inner write back */
|
||
|
|
MPU->RBAR = ARM_MPU_RBAR(7, 0x20200000U);
|
||
|
|
MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 0, 0, 1, 1, 0, ARM_MPU_REGION_SIZE_512KB);
|
||
|
|
|
||
|
|
/* Region 8 setting: Memory with Normal type, not shareable, outer/inner write back */
|
||
|
|
MPU->RBAR = ARM_MPU_RBAR(8, 0x20280000U);
|
||
|
|
MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 0, 0, 1, 1, 0, ARM_MPU_REGION_SIZE_256KB);
|
||
|
|
|
||
|
|
/* Region 9 setting: Memory with Normal type, not shareable, outer/inner write back */
|
||
|
|
MPU->RBAR = ARM_MPU_RBAR(9, 0x80000000U);
|
||
|
|
MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 0, 0, 1, 1, 0, ARM_MPU_REGION_SIZE_32MB);
|
||
|
|
|
||
|
|
while ((size >> i) > 0x1U)
|
||
|
|
{
|
||
|
|
i++;
|
||
|
|
}
|
||
|
|
|
||
|
|
if (i != 0)
|
||
|
|
{
|
||
|
|
/* The MPU region size should be 2^N, 5<=N<=32, region base should be multiples of size. */
|
||
|
|
assert(!(nonCacheStart % size));
|
||
|
|
assert(size == (uint32_t)(1 << i));
|
||
|
|
assert(i >= 5);
|
||
|
|
|
||
|
|
/* Region 10 setting: Memory with Normal type, not shareable, non-cacheable */
|
||
|
|
MPU->RBAR = ARM_MPU_RBAR(10, nonCacheStart);
|
||
|
|
MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 1, 0, 0, 0, 0, i - 1);
|
||
|
|
}
|
||
|
|
|
||
|
|
/* Region 10 setting: Memory with Device type, not shareable, non-cacheable */
|
||
|
|
MPU->RBAR = ARM_MPU_RBAR(11, 0x40000000);
|
||
|
|
MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 2, 0, 0, 0, 0, ARM_MPU_REGION_SIZE_4MB);
|
||
|
|
|
||
|
|
/* Region 12 setting: Memory with Device type, not shareable, non-cacheable */
|
||
|
|
MPU->RBAR = ARM_MPU_RBAR(12, 0x42000000);
|
||
|
|
MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 2, 0, 0, 0, 0, ARM_MPU_REGION_SIZE_1MB);
|
||
|
|
|
||
|
|
/* Enable MPU */
|
||
|
|
ARM_MPU_Enable(MPU_CTRL_PRIVDEFENA_Msk | MPU_CTRL_HFNMIENA_Msk);
|
||
|
|
|
||
|
|
/* Enable I cache and D cache */
|
||
|
|
SCB_EnableDCache();
|
||
|
|
SCB_EnableICache();
|
||
|
|
}
|