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52 Commits

Author SHA1 Message Date
rogday
9cd5a0a1e6
Merge pull request #21884 from rogday:cuda_cleanup 
Fix CUDA compilation issues and adjust thresholds.

* Fix CUDA compilation issues and adjust thresholds.

* add conformance tests to denylist
 2022-04-19 16:40:25 +00:00
zihaomu
e36948cfbc add ONNX OP sign, shrink and reciprocal 2022-04-07 15:32:12 +08:00
luz paz
8e8e4bbabc dnn: fix various dnn related typos 
Fixes source comments and documentation related to dnn code.
 2022-03-23 18:12:12 -04:00
Smirnov Egor
71a22e45b0 add celu, hardsigmoid, selu, thresholdedrelu layers 2021-12-18 03:19:54 +03:00
Smirnov Egor
1bd382c1d0 Add acos, acosh, asin, asinh, atan, atanh, cos, cosh, erf, hardswish, sin, sinh, softplus, softsign, tan layers 2021-12-17 18:19:40 +03:00
Smirnov Egor
4995aecd62 add alpha parameter to ELU 2021-11-30 14:43:18 +03:00
Supernovae
b594ed99b8
Merge pull request #20933 from shubham-shahh:master 
Improved overall readability of the code

* grid_nms.cu: minor fix-ups

* Update grid_stride_range.hpp

* Update tf_importer.cpp
 2021-11-28 12:54:29 +00:00
Smirnov Egor
1feb3838b5 add Ceil, Floor, Log, Round, Sqrt, Not, Equal, Less, Greater 2021-10-15 16:02:46 +03:00
Smirnov Egor
9c84749e2c backport YOLOv4x-mish new_coords CUDA implementation 2021-10-08 14:14:49 +03:00
YashasSamaga
505dde09de support broadcasting in eltwise ops 2021-10-04 12:38:45 +05:30
rogday
38b9ec7a18
Merge pull request #20682 from rogday:min 
* Add Min layer to CPU, OpenCL, Halide, Inference Engine, NGraph and CUDA

* fix indentation

* add min to fusion and halide tests; fix doc
 2021-09-22 15:17:37 +03:00
Alexander Alekhin
c89084e6b7 Merge pull request #19223 from YashasSamaga:cuda4dnn-halfpix-linear-resize 2021-03-30 13:19:41 +00:00
SamFC10
6111935835 Added exp layer 2021-02-20 22:16:00 +05:30
Sergei Slashchinin
ea41f89b40
Merge pull request #19058 from sl-sergei:cuda_1d 
Conv1D and Pool1D for CUDA backend

* CUDA-independent changes

* Add Conv1D and Pool1D for CUDA backend

* CUDA-independent changes

* Fix typo

* fix comment

* Update fix

* make changes more correct for pooling layer

* Minor fixes for review

* Split skip blocks
 2021-01-21 22:16:56 +00:00
YashasSamaga
8c74d7e4fa add half pixel centers and align corners param 2020-12-27 15:05:39 +05:30
YashasSamaga
f0149cdae2 fix compile-time errors, disable unsupported tests 2020-08-09 14:43:20 +05:30
YashasSamaga
a3106d424b add MVNOp 2020-08-02 12:44:35 +05:30
YashasSamaga
ae293f27cf add DetectionOutputOp 2020-07-29 12:28:00 +05:30
Yashas Samaga B L
d0e6d2438c
Merge pull request #17363 from YashasSamaga:cuda4dnn-eltwise-fusion2 
cuda4dnn(conv): fuse eltwise with convolutions

* fuse eltwise with convolutions

* manually rebase to avoid bad git merge
 2020-07-09 16:02:21 +03:00
YashasSamaga
cbdaa93e54 reduce slice, concat to copy; enable more concat fusions 2020-07-05 20:52:35 +05:30
YashasSamaga
6573b9ace0 use fp32 mish for fp16 mish 2020-06-22 19:09:36 +05:30
Yashas Samaga B L
9ba5581d17
Merge pull request #17534 from YashasSamaga:cuda4dnn-remove-unused-funcs 
cuda4dnn: reduce CUDA version requirements to at least CUDA 9.2

* remove half2 specializations

* do not remove atomicAdd for half in CUDA 10 and below

* remove fp16.hpp
 2020-06-17 09:07:52 +00:00
YashasSamaga
87ab4ee567 improve mish performance and accuracy 2020-06-13 16:53:27 +05:30
YashasSamaga
3c35b563d7 add scale_x_y parameter to region 2020-05-10 16:53:28 +05:30
Yashas Samaga B L
d981d04c76
Merge pull request #17200 from YashasSamaga:cuda4dnn-general-opt1 
cuda4dnn: optimizations for swish, mish, sigmoid, region, resize based ops, transpose, identity-conv fusion

* bunch of optimizations

* more accurate implementation for mish
 2020-05-09 17:20:30 +00:00
Yashas Samaga B L
8808aaccff
Merge pull request #16658 from YashasSamaga:cuda4dnn-refactor-activations 
cuda4dnn(activations, eltwise, scale_shift): refactor to reduce code duplication

* refactor activations

* refactor eltwise kernels

* move all functors to functors.hpp

* remove bias1 and scale1 kernels
 2020-02-29 11:46:14 +03:00
Alexander Alekhin
2ced568d34 Merge pull request #16220 from YashasSamaga:cuda4dnn-roi-pooling-test_fix-optim 2020-01-29 20:57:15 +00:00
Julien Maille
a696348ec5 FIX: disable dnn cuda input_shortcut on _half for CC<5.3 2020-01-17 14:21:25 +01:00
Yashas Samaga B L
d85e67d3ec Merge pull request #16063 from YashasSamaga:cuda4dnn-shortcut-unequal 
support eltwise sum with different number of input channels in CUDA backend

* add shortcut primitive

* add offsets in shortcut kernel

* skip tests involving more than two inputs

* remove redundant modulus operation

* support multiple inputs

* remove whole file indentation

* skip acc in0 trunc test if weighted

* use shortcut iff channels are unequal
 2020-01-16 21:54:00 +03:00
Julien
ced3df73da Fix: rsqrt(float) was improperly put in the ifdef for half 2020-01-16 09:21:50 +01:00
YashasSamaga
fd369a5004 fix and optimize ROIPooling 2020-01-15 22:53:48 +05:30
Julien
4e2ef8c8f5 Merge pull request #16218 from JulienMaille:cuda-dnn-for-older-gpus 
Enable cuda4dnn on hardware without support for __half

* Enable cuda4dnn on hardware without support for half (ie. compute capability < 5.3)

Update CMakeLists.txt

Lowered minimum CC to 3.0

* UPD: added ifdef on new copy kernel

* added fp16 support detection at runtime

* Clarified #if condition on atomicAdd definition

* More explicit CMake error message
 2020-01-15 18:28:37 +03:00
Alexander Alekhin
1f2b2c5242 Merge pull request #16230 from YashasSamaga:cuda4dnn-fp-conversion 2020-01-05 11:59:33 +00:00
YashasSamaga
48eecafc89 simplify code to help MSVC 19.10 and lower 2019-12-30 23:02:17 +05:30
YashasSamaga
01f97f150c perfor fp conversions on GPU 2019-12-30 00:05:39 +05:30
Alexander Alekhin
9ec3d76b21 Merge pull request #16241 from bwignall:typo 2019-12-27 16:18:57 +00:00
Brian Wignall
659ffaddb4 Fix spelling typos 2019-12-26 06:45:03 -05:00
YashasSamaga
16bc505d26 improve reduction logic and add fast transpose kernel 2019-12-24 00:23:45 +05:30
Alexander Alekhin
b8e0898c7c Merge pull request #16082 from YashasSamaga:cuda4dnn-roi-pooling 2019-12-18 14:41:58 +00:00
Yashas Samaga B L
17c485eb03 Merge pull request #16092 from YashasSamaga:cuda4dnn-conv-act-fuse 
cuda4dnn: fuse activations with convolutions

* fuse ReLU, ReLU6, TanH, Sigmoid with conv

* fix OpenCL errors

* improve ReLU, add power, swish and mish

* fix missing fusion entries

* fix handling of unsetAttached

* remove whole file indentation

* optimize power = 1.0, use IDENTITY instead of NONE

* handle edge case: change backend and then clear
 2019-12-14 22:26:58 +03:00
Yashas Samaga B L
3fddd3bf93 Merge pull request #16069 from YashasSamaga:cuda4dnn-crop_and_resize 
add CropAndResize layer for CUDA backend

* add CropAndResize layer

* process multiple channels per iteration
 2019-12-09 22:26:58 +03:00
Alexander Alekhin
b505cf84de Merge pull request #16096 from YashasSamaga:cuda4dnn-region-optimize 2019-12-09 14:34:48 +00:00
Yashas Samaga B L
476a02739e Merge pull request #16097 from YashasSamaga:cuda4dnn-optimize-resize-bilinear 
cuda4dnn(resize): process multiple channels each iteration

* resize bilinear: process multiple chans. per iter.

* remove unused headers

* correct dispatch logic

* resize_nn: process multiple chans. per iter.
 2019-12-09 17:31:27 +03:00
Yashas
dd3f517fe9 optimize region kernels 2019-12-08 21:03:30 +05:30
Alexander Alekhin
202ba124a5 Merge pull request #16087 from YashasSamaga:cuda4dnn-eltwise-div 2019-12-06 18:33:55 +00:00
YashasSamaga
a91eca6ec2 add DIV support to EltwiseOp 2019-12-06 21:28:36 +05:30
YashasSamaga
9b8ddba4d1 add ROIPoolingOp 2019-12-06 18:19:37 +05:30
YashasSamaga
fbb3f64a1a fix expm1 and log1p for __half/__half2 2019-12-03 15:25:35 +05:30
Manjunath Bhat
78c5e41c23 Merge pull request #15808 from thebhatman:Mish_swish 
* Added Swish and Mish activations

* Fixed whitespace errors

* Kernel implementation done

* Added function for launching kernel

* Changed type of 1.0

* Attempt to add test for Swish and Mish

* Resolving type mismatch for log

* exp from device

* Use log1pexp instead of adding 1

* Added openCL kernels
 2019-12-02 00:06:17 +03:00
Brian Wignall
9276f1910b Fix some typos 2019-11-25 19:55:07 -05:00